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1. 发明授权

US06812536B2 MOSFET with graded gate oxide layer 失效
标题翻译：具有梯度栅氧化层的MOSFET
公开(公告)号：US06812536B2
公开(公告)日：2004-11-02
申请号：US10383753
申请日：2003-03-10
申请人： Shuichi Ueno , Yukio Nishida , Hiroshi Umeda , Kenichi Ohto , Takashi Terauchi , Shigeru Shiratake , Akinori Kinugasa
发明人： Shuichi Ueno , Yukio Nishida , Hiroshi Umeda , Kenichi Ohto , Takashi Terauchi , Shigeru Shiratake , Akinori Kinugasa
IPC分类号： H01L2976
CPC分类号： H01L29/42368 , H01L21/28247
摘要： A smile oxide film, serving as a gate oxide film, is formed under a three-layer poly-metal gate consisting of a doped polysilicon layer, a tungsten layer, and a SiON layer. The smile oxide film has a first region located beneath an edge of the poly-metal gate and a second region located beneath a central portion of the poly-metal gate. A film thickness of the first region is larger than a film thickness of the second region. An anti-oxidizing film, having a small oxygen diffusion rate compared with the polysilicon layer, entirely covers the poly-metal gate without exposing.
摘要翻译：作为栅极氧化膜的微笑氧化膜形成在由掺杂多晶硅层，钨层和SiON层构成的三层多金属栅极的下方。微笑氧化膜具有位于多金属栅极的边缘下方的第一区域和位于多金属栅极的中心部分下方的第二区域。第一区域的膜厚度大于第二区域的膜厚度。与多晶硅层相比具有小的氧扩散速率的抗氧化膜完全覆盖多金属栅极而不暴露。

2. 发明授权

US06461934B2 Method of manufacturing semiconductor device having trench type element isolation regions 失效
标题翻译：制造具有沟槽型元件隔离区域的半导体器件的方法
公开(公告)号：US06461934B2
公开(公告)日：2002-10-08
申请号：US09862311
申请日：2001-05-23
申请人： Yukio Nishida , Shuichi Ueno , Masashi Kitazawa
发明人： Yukio Nishida , Shuichi Ueno , Masashi Kitazawa
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： Trench isolation regions of different depths are formed through a simple manufacturing process, and reliability of a semiconductor device is increased. Trenches (103a, 103b) of different widths are formed on a semiconductor substrate (101) on which an underlying film (104) such as a silicon oxide film and a mask material (105) such as a silicon nitride film are formed. Then, an insulating film such as a silicon oxide film is deposited over the entire surface to such a degree that the narrower trench (103a) is filled up. At this time, the wider trench (103b) has an unfilled space in its central portion. a The surface of the substrate (101) is then vertically etched back until it is exposed in the trench 103b. With insulating films (106a, 106b) in the trenches (103a, 103b) as a mask, the surface of the substrate (101) is anisotropically etched vertically to form a deeper bottom (103c) in the trench (103b). After that, the surface is planarizedby depositing an insulating film in the unfilled space of the trench (103b).
摘要翻译：通过简单的制造工艺形成不同深度的沟槽隔离区域，并且增加了半导体器件的可靠性。在半导体衬底（101）上形成不同宽度的沟槽（103a，103b），在其上形成诸如氧化硅膜的底层膜（104）和诸如氮化硅膜的掩模材料（105）。然后，在整个表面上沉积诸如氧化硅膜的绝缘膜，使得填充较窄的沟槽（103a）的程度。此时，较宽的沟槽（103b）在其中央部分具有未填充的空间。 a然后将衬底（101）的表面垂直蚀刻回直到其暴露在沟槽103b中。以沟槽（103a，103b）中的绝缘膜（106a，106b）作为掩模，垂直地各向异性地蚀刻衬底（101）的表面，以在沟槽（103b）中形成更深的底部（103c）。之后，通过在沟槽（103b）的未填充空间中沉积绝缘膜来平坦化表面。

3. 发明授权

US06335252B1 Semiconductor device manufacturing method 有权
标题翻译：半导体器件制造方法
公开(公告)号：US06335252B1
公开(公告)日：2002-01-01
申请号：US09564550
申请日：2000-05-04
申请人： Toshiyuki Oishi , Yukio Nishida , Hirokazu Sayama , Hidekazu Oda
发明人： Toshiyuki Oishi , Yukio Nishida , Hirokazu Sayama , Hidekazu Oda
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： An MIS transistor manufacturing method which can prevent unwanted diffusion of extensions caused by the drive to the source/drain so that the diffusion of the source/drain and the diffusion of the extensions can independently be controlled so as to obtain optimum structure for each. Source/drain are formed by ion implantation using, as a mask, L-shaped silicon nitride films formed on sides of a gate electrode and silicon oxide films covering the silicon nitride films. The silicon oxide films are then removed leaving the silicon nitride films. Impurity ions are then ion-implanted into the main surface of the silicon substrate through the silicon nitride films. Since the silicon nitride films are thicker in the vicinity of the gate electrode and thinner in the vicinity of the source/drain, this process forms extensions penetrating under the gate electrode for a small distance.
摘要翻译：一种MIS晶体管制造方法，其可以防止由源极/漏极的驱动引起的延伸部的不期望的扩散，从而可以独立地控制源极/漏极的扩散和扩展部的扩散，从而获得每个的最佳结构。作为掩模，通过离子注入形成源极/漏极，形成在栅电极的侧面上的L形氮化硅膜和覆盖氮化硅膜的氧化硅膜。然后去除氧化硅膜，留下氮化硅膜。然后通过氮化硅膜将杂质离子离子注入硅衬底的主表面。由于氮化硅膜在栅电极附近较厚并且在源极/漏极附近较薄，所以该工艺形成了在栅电极下方一小段距离的延伸。

4. 发明授权

US06864128B2 Manufacturing method for a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06864128B2
公开(公告)日：2005-03-08
申请号：US10623563
申请日：2003-07-22
申请人： Yukio Nishida , Kazunobu Ohta
发明人： Yukio Nishida , Kazunobu Ohta
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/4763 , H01L21/8234 , H01L21/8238 , H01L21/84 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/82385 , H01L21/28114 , H01L21/823842 , H01L21/823864 , H01L29/42376
摘要： A gate insulating film 4, two polysilicon films 5 and 7, and a silicon nitride film 9 are successively laminated on a semiconductor substrate 1 in this order. Each of the polysilicon films 5 and 7 contains phosphorus. The polysilicon film 5 has a region having a phosphorus concentration higher than that of the polysilicon film 7. Gate electrodes 10n, 10p, 40n, and 40p are formed on the gate insulating film 4 by partly etching the polysilicon films 5 and 7 and the silicon nitride film 9. In this case, the etching rate of the region of the polysilicon film 5, having a phosphorus concentration higher than that of the polysilicon film 7, is higher than that of the polysilicon film 7. Due to this difference, notches are formed at the bottom portions on side surfaces of respective gate electrodes 10p, 40n, and 40p.
摘要翻译：依次将栅极绝缘膜4，两个多晶硅膜5和7以及氮化硅膜9依次层叠在半导体基板1上。多晶硅膜5和7中的每一个都含有磷。多晶硅膜5具有比多晶硅膜7的磷浓度高的区域。通过部分蚀刻多晶硅膜5和7，在栅极绝缘膜4上形成栅电极10n，10p，40n和40p，并且硅在这种情况下，具有比多晶硅膜7高的磷浓度的多晶硅膜5的区域的蚀刻速率高于多晶硅膜7的蚀刻速率。由于这种差异，凹口是形成在各个栅电极10p，40n和40p的侧表面的底部。

5. 发明授权

US06344388B1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06344388B1
公开(公告)日：2002-02-05
申请号：US09325803
申请日：1999-06-04
申请人： Toshiyuki Oishi , Yukio Nishida , Hirokazu Sayama
发明人： Toshiyuki Oishi , Yukio Nishida , Hirokazu Sayama
IPC分类号： H01L218236
CPC分类号： H01L27/10894 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28052 , H01L21/28114 , H01L21/76232 , H01L27/1052 , H01L27/10873 , H01L29/665 , H01L29/6656 , H01L29/66628
摘要： In a method of manufacturing a semiconductor device capable of reducing gate resistance by increasing the width of a conductive layer formed on a gate electrode without increasing the gate length, an extension is formed in an upper surface of a silicon substrate, and thereafter a silicon oxide film and a silicon nitride film are deposited on the overall surface. Then, the silicon nitride film and the silicon oxide film are anisotropically etched in this order. Then, another silicon oxide film is deposited on the overall surface and thereafter anisotropically etched. Then, ion implantation is performed through a gate electrode and a side wall serving as masks, to form an impurity region. Silicon is grown under conditions having selectivity for a silicon oxide film, to form a silicon growth layer. Then, cobalt is deposited on the overall surface and thereafter heat treatment is performed to form a cobalt silicide layer. Thereafter unreacted cobalt is removed.
摘要翻译：在通过增加形成在栅电极上的导电层的宽度而不增加栅极长度的方式制造能够降低栅极电阻的方法中，在硅衬底的上表面中形成延伸部分，然后将氧化硅膜和氮化硅膜沉积在整个表面上。然后，依次对氮化硅膜和氧化硅膜进行各向异性蚀刻。然后，将另一氧化硅膜沉积在整个表面上，然后各向异性蚀刻。然后，通过栅极电极和用作掩模的侧壁进行离子注入，以形成杂质区域。硅在具有对氧化硅膜的选择性的条件下生长，以形成硅生长层。然后，在整个表面上沉积钴，然后进行热处理以形成硅化钴层。此后除去未反应的钴。

6. 发明申请

US20140035055A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：半导体集成电路装置及制造半导体集成电路装置的方法
公开(公告)号：US20140035055A1
公开(公告)日：2014-02-06
申请号：US14111549
申请日：2012-04-09
申请人： Hirofumi Shinohara , Yukio Nishida , Katsuyuki Horita , Tomohiro Yamashita , Hidekazu Oda
发明人： Hirofumi Shinohara , Yukio Nishida , Katsuyuki Horita , Tomohiro Yamashita , Hidekazu Oda
IPC分类号： H01L27/088 , H01L29/66
CPC分类号： H01L27/088 , H01L21/823842 , H01L21/823878 , H01L29/66477
摘要： MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment.The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.
摘要翻译： 32nm技术节点之后的MISFET具有高k栅极绝缘膜和金属栅电极。这样的MISFET的问题是，随后的高温热处理，n-MISFET和p-MISFET的阈值电压的绝对值不可避免地增加。因此，通过在High-k栅极绝缘膜上形成各种阈值电压调整金属膜并将膜分量从它们引入到高k栅极绝缘膜中来控制阈值电压。然而，本发明人揭示了引入到n-MISFET的高k栅极绝缘膜中的镧等可能通过随后的热处理转移到STI区域。根据本发明的半导体集成电路器件在n-MISFET的栅极堆叠的下方和周围的元件隔离区域的表面部分中设置有N沟道阈值电压调节元件向外扩散防止区域。

7. 发明申请

US20080308869A1 SEMICONDUCTOR DEVICE WHICH HAS MOS STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有MOS结构的半导体器件及其制造方法
公开(公告)号：US20080308869A1
公开(公告)日：2008-12-18
申请号：US12194631
申请日：2008-08-20
申请人： Hidekazu ODA , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
发明人： Hidekazu ODA , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
IPC分类号： H01L29/00
CPC分类号： H01L21/823842
摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.
摘要翻译：可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱有了这个。当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

8. 发明申请

US20070111427A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070111427A1
公开(公告)日：2007-05-17
申请号：US11599382
申请日：2006-11-15
申请人： Tomohiro Yamashita , Yukio Nishida , Hidekazu Oda
发明人： Tomohiro Yamashita , Yukio Nishida , Hidekazu Oda
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/28097 , H01L21/823835 , H01L21/823864 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/7842 , H01L29/7843
摘要： The semiconductor device which can apply the stress application technology to a channel part by a liner film to MISFET including a full silicidation gate electrode, and its manufacturing method are realized. The first liner silicon nitride film is formed on the semiconductor substrate MISFET formed. Insulating films, such as a silicon oxide film, are formed on the first liner silicon nitride film so that it may fully fill up the side of a gate electrode. Next, flattening processing is performed to an insulating film and the first liner silicon nitride film, and a polysilicon gate electrode is exposed. An insulating film is removed leaving the first liner silicon nitride film. The full silicidation of the exposed gate electrode is done, and the second liner silicon nitride film that covers the first liner silicon nitride film and the exposed full silicidation gate electrode is formed.
摘要翻译：实现了通过衬垫膜将应力施加技术应用于包括全硅化物栅电极的MISFET在内的半导体器件及其制造方法。第一衬里氮化硅膜形成在形成的半导体衬底MISFET上。在第一衬垫氮化硅膜上形成诸如氧化硅膜的绝缘膜，使得其可以完全填满栅电极的侧面。接着，对绝缘膜进行平坦化处理，露出第一衬垫氮化硅膜和多晶硅栅电极。除去留下第一衬里氮化硅膜的绝缘膜。完成暴露的栅电极的全硅化，形成覆盖第一衬垫氮化硅膜和暴露的全硅化栅电极的第二衬垫氮化硅膜。

9. 发明申请

US20070007602A1 Semiconductor device which has MOS structure and method of manufacturing the same 审中-公开
标题翻译：具有MOS结构的半导体器件及其制造方法
公开(公告)号：US20070007602A1
公开(公告)日：2007-01-11
申请号：US11478669
申请日：2006-07-03
申请人： Hidekazu Oda , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
发明人： Hidekazu Oda , Takahisa Eimori , Jiro Yugami , Takahiro Maruyama , Tomohiro Yamashita , Yukio Nishida , Shinichi Yamanari , Takashi Hayashi , Kenichi Mori
IPC分类号： H01L29/94
CPC分类号： H01L21/823842
摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.
摘要翻译：可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱有了这个。当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

10. 发明授权

US06600195B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06600195B1
公开(公告)日：2003-07-29
申请号：US09637870
申请日：2000-08-15
申请人： Yukio Nishida , Hirokazu Sayama , Hidekazu Oda , Toshiyuki Oishi
发明人： Yukio Nishida , Hirokazu Sayama , Hidekazu Oda , Toshiyuki Oishi
IPC分类号： H01L2976
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/823412 , H01L21/823456 , H01L29/66492 , H01L29/66537 , H01L29/7833
摘要： A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effect transistor includes a gate electrode, source and drain regions, and a channel region. The channel region includes a pair of lightly doped impurity regions having a relatively low impurity concentration as well as a heavily doped impurity region located between the lightly doped impurity regions and having a relatively high impurity concentration.
摘要翻译：提供能够防止阈值电压变化并具有高可靠性的半导体器件。半导体器件包括具有半导体区域的半导体衬底和场效应晶体管。场效应晶体管包括栅电极，源极和漏极区以及沟道区。沟道区包括杂质浓度相对较低的一对轻掺杂杂质区，以及位于轻掺杂杂质区之间并具有较高杂质浓度的重掺杂杂质区。

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