专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5706461A Method and apparatus for implementing virtual memory having multiple selected page sizes 失效
公开(公告)号：US5706461A
公开(公告)日：1998-01-06
申请号：US638223
申请日：1996-04-26
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Kevin Gerard Plotz , Fadi-Christian E. Safi , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Kevin Gerard Plotz , Fadi-Christian E. Safi , Albert Alfonse Slane
IPC分类号： G06F12/02 , G06F12/10 , G11B25/04 , G11B33/12 , G06F12/00 , G06F12/04
CPC分类号： G06F12/10 , G06F12/1009 , G11B25/043 , G06F12/0292 , G06F2212/652 , G11B33/12
摘要： A method and apparatus for implementing virtual memory having multiple selected page sizes are provided. A virtual address includes a map index and a frame offset. A selector mechanism receives the virtual address frame offset and generates an offset and index. A frame map table indexes the virtual address map index and the selector generated index and generates a base address. The frame map table generated base address and the selector generated offset are combined to provide a physical address.

2. 发明授权

US06765911B1 Communications adapter for implementing communications in a network and providing multiple modes of communications 失效
标题翻译：用于在网络中实现通信并提供多种通信模式的通信适配器
公开(公告)号：US06765911B1
公开(公告)日：2004-07-20
申请号：US09243858
申请日：1999-02-03
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
IPC分类号： H04L1256
CPC分类号： H04L47/58 , H04L12/5601 , H04L47/50 , H04L2012/5652 , H04L2012/5679
摘要： A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.
摘要翻译：提供了一种用于在通信网络中实现通信的方法和装置。用于实现通信的装置包括到通信网络的系统接口。调度器调度入队单元和要发送的入队帧。分段器将帧和小区划分成应用于媒体适配块的小区或帧，以在多个模式中选择的一个模式中进行传输。

3. 发明授权

US06498782B1 Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation 有权
标题翻译：通信方式和千兆以太网通信适配器提供服务质量和接收机连接速度差异化
公开(公告)号：US06498782B1
公开(公告)日：2002-12-24
申请号：US09243956
申请日：1999-02-03
申请人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
发明人： Mark William Branstad , Jonathan William Byrn , Gary Scott Delp , Philip Lynn Leichty , Todd Edwin Leonard , Gary Paul McClannahan , John Emery Nordman , Kevin Gerard Plotz , John Handley Shaffer , Albert Alfonse Slane
IPC分类号： G06F1100
CPC分类号： H04L47/24 , H04L12/40032 , H04L12/4015 , H04L12/413 , H04L47/10 , H04L47/22 , H04L47/50 , H04L47/568 , H04L47/6215
摘要： A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.
摘要翻译：提供了一种用于实现通信网络中的通信的方法和千兆以太网通信适配器。定义要发送的数据的传输队列。为传输队列设置传输速率。要发送的数据在传输队列中排队。传输队列可以被划分为多个优先级队列，例如使用时轮，并为每个传输队列设置一个传输速率。

4. 发明授权

US06181705B2 System and method for management a communications buffer 失效
标题翻译：用于管理通信缓冲区的系统和方法
公开(公告)号：US06181705B2
公开(公告)日：2001-01-30
申请号：US08691803
申请日：1996-08-14
申请人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
发明人： Mark William Branstad , Brad Louis Brech , Jonathan William Byrn , Gary Scott Delp , Rafael M. Montalvo
IPC分类号： H04L1308
CPC分类号： H04L49/901 , H04L49/90 , H04L49/9052
摘要： A network buffer memory is divided into pools of locations including a plurality of tinygram contiguous sections and a plurality of jumbogram contiguous sections. The tinygram contiguous sections available for storage of packets are listed in a list of tinygram pointers. The jumbogram contiguous sections available for storage of packets are also listed in a list of jumbogram pointers. A threshold for distinguishing the packets as tinygrams and jumbograms is programmed. As packets are received, they are measured against the threshold. Responsive to detection of an end of packet condition prior to reaching the threshold, storing the packet in a tinygram contiguous section. Otherwise, the packet is stored in a jumbogram contiguous section. Availability of sections is determined by query to the FIFO lists of pointers.
摘要翻译：网络缓冲存储器被划分为包括多个小节连续部分和多个巨型图连续部分的位置池。可用于存储数据包的tinygram连续区段列在tinygram指针列表中。可用于存储数据包的巨型连续段也列在巨型指针列表中。用于将分组区分为微小图形和巨型图形的阈值被编程。当接收到数据包时，将根据阈值进行测量。响应于在到达阈值之前检测到分组状态的结束，将分组存储在微小的连续部分中。否则，数据包存储在巨型图连续部分。部分的可用性是通过查询指针的FIFO列表来确定的。

5. 发明授权

US5764712A Phase locked loop circuit having automatic range setting logic 失效
标题翻译：锁相环电路具有自动量程设定逻辑
公开(公告)号：US5764712A
公开(公告)日：1998-06-09
申请号：US634504
申请日：1996-04-18
申请人： Mark William Branstad , Philip Lynn Leichty , Brian Andrew Schuelke
发明人： Mark William Branstad , Philip Lynn Leichty , Brian Andrew Schuelke
IPC分类号： H03L7/10 , H03L7/113
CPC分类号： H03L7/10 , H03L7/113 , Y10S331/02
摘要： A method for setting a locking frequency operating range of the phase locked loop (PLL) circuit and a phase locked loop (PLL) circuit are provided with range select logic for detecting an unknown reference clock frequency and for setting a locking frequency operating range of the phase locked loop. First a bypass mode for the phase locked loop (PLL) circuit is set. An unknown reference clock frequency is applied to a first counter. A known oscillator clock frequency is applied to a second counter. The first and second counters are reset and a timeout value of the second counter is identified. A first counter count value is compared with precalculated constant values. A set of range bits are latched responsive to said compared values. Two consecutive sets of latched range bits are compared and the steps repeated until a match of two consecutive sets of latched range bits is identified. The matching latched range bits are applied to a programmable range select input of the phase locked loop (PLL) circuit.
摘要翻译：用于设置锁相环（PLL）电路和锁相环（PLL）电路的锁定频率工作范围的方法设置有用于检测未知参考时钟频率的范围选择逻辑，并且用于设置锁相环锁相环。首先设置锁相环（PLL）电路的旁路模式。将未知的参考时钟频率应用于第一个计数器。已知的振荡器时钟频率被施加到第二计数器。第一和第二计数器被复位，并且识别出第二计数器的超时值。将第一计数器计数值与预先计算的常数值进行比较。响应于所述比较值而锁存一组范围位。比较两个连续的锁存范围比特组，并重复步骤，直到两个连续的锁存范围比特组的匹配被识别。匹配的锁存范围位被应用于锁相环（PLL）电路的可编程范围选择输入。

6. 发明授权

US06519716B1 Electronic device initialization with dynamic selection of access time for non-volatile memory 失效
标题翻译：电子设备初始化，动态选择非易失性存储器的访问时间
公开(公告)号：US06519716B1
公开(公告)日：2003-02-11
申请号：US09400587
申请日：1999-09-22
申请人： Mark William Branstad
发明人： Mark William Branstad
IPC分类号： G06F1122
CPC分类号： G11C29/028 , G06F11/2284 , G11C16/04 , G11C16/20 , G11C29/50 , G11C29/50012
摘要： A circuit arrangement and method of initializing an electronic device dynamically test a non-volatile memory prior to retrieving initialization program code to select an operational access time at which the initialization program code can be reliably retrieved from the non-volatile memory. Specifically, at least one test access is performed with the non-volatile memory to determine a satisfactory access time at which the non-volatile memory correctly processes the test access. Thereafter, initialization program code is retrieved from the non-volatile memory using an operational access time selected based upon the determined satisfactory access time. As such, through judicious selection of an appropriate operational access time, non-volatile memory devices having differing performance capabilities can be accessed in an optimal manner using the same memory control logic design, and without the need for specific customization or program code modifications.
摘要翻译：初始化电子设备的电路装置和方法在检索初始化程序代码之前动态测试非易失性存储器，以选择可以从非易失性存储器可靠地检索初始化程序代码的操作访问时间。具体地，使用非易失性存储器执行至少一个测试访问以确定非易失性存储器正确处理测试访问的令人满意的访问时间。此后，使用基于所确定的令人满意的访问时间选择的操作访问时间，从非易失性存储器检索初始化程序代码。因此，通过适当地选择适当的操作访问时间，可以以最佳方式使用相同的存储器控制逻辑设计来访问具有不同性能能力的非易失性存储器件，并且不需要特定的定制或程序代码修改。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式