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1. 发明申请

US20110209155A1 SPECULATIVE THREAD EXECUTION WITH HARDWARE TRANSACTIONAL MEMORY 有权
标题翻译：具有硬件交互式存储器的线性螺纹执行
公开(公告)号：US20110209155A1
公开(公告)日：2011-08-25
申请号：US12711352
申请日：2010-02-24
申请人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
发明人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
IPC分类号： G06F9/46 , G06F12/08 , G06F12/00
CPC分类号： G06F9/466 , G06F9/3842 , G06F9/467 , G06F9/4843 , G06F9/4881 , G06F9/5016 , G06F9/52 , G06F12/0862
摘要： In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.
摘要翻译：在一个实施例中，如果自线程具有多于一个冲突，则自线程的事务被中止并重新启动。如果自线程只有一个冲突，并且自线程的敌方线程有多个冲突，则自线程的事务被提交。如果自线程只与敌方线程冲突，敌方线程只与自线程冲突，自线程的密钥优先级高于敌方线程的密钥，则自线程的事务被提交。如果自线程只与敌方线程相冲突，敌方线程只会与自身线程冲突，自线程的密钥优先级低于敌方线程的密钥，自身线程的事务中止。

2. 发明授权

US08438568B2 Speculative thread execution with hardware transactional memory 有权
标题翻译：使用硬件事务内存的推测线程执行
公开(公告)号：US08438568B2
公开(公告)日：2013-05-07
申请号：US12711352
申请日：2010-02-24
申请人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
发明人： Mark E. Giampapa , Thomas M. Gooding , Raul E. Silvera , Kai-Ting Amy Wang , Peng Wu , Xiaotong Zhuang
IPC分类号： G06F9/46 , G06F7/00 , G06F13/00
CPC分类号： G06F9/466 , G06F9/3842 , G06F9/467 , G06F9/4843 , G06F9/4881 , G06F9/5016 , G06F9/52 , G06F12/0862
摘要： In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.
摘要翻译：在一个实施例中，如果自线程具有多于一个冲突，则自线程的事务被中止并重新启动。如果自线程只有一个冲突，并且自线程的敌方线程有多个冲突，则自线程的事务被提交。如果自线程只与敌方线程冲突，敌方线程只与自线程冲突，自线程的密钥优先级高于敌方线程的密钥，则自线程的事务被提交。如果自线程只与敌方线程相冲突，敌方线程只会与自身线程冲突，自线程的密钥优先级低于敌方线程的密钥，自身线程的事务中止。

3. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

4. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

5. 发明授权

US08140925B2 Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan 失效
标题翻译：通过同步时钟停止和扫描来调试集成电路芯片的方法和装置
公开(公告)号：US08140925B2
公开(公告)日：2012-03-20
申请号：US11768791
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Matthew R. Ellavsky , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Lance G. Hehenberger , Martin Ohmacht
发明人： Ralph E. Bellofatto , Matthew R. Ellavsky , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Lance G. Hehenberger , Martin Ohmacht
IPC分类号： G01R31/28 , G06F1/12
CPC分类号： G06F11/2236
摘要： An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.
摘要翻译：一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

6. 发明授权

US07716407B2 Executing application function calls in response to an interrupt 有权
标题翻译：执行应用程序函数调用以响应中断
公开(公告)号：US07716407B2
公开(公告)日：2010-05-11
申请号：US11968720
申请日：2008-01-03
申请人： Gheorghe Almasi , Charles J. Archer , Mark E. Giampapa , Thomas M. Gooding , Philip Heidelberger , Jeffrey J. Parker
发明人： Gheorghe Almasi , Charles J. Archer , Mark E. Giampapa , Thomas M. Gooding , Philip Heidelberger , Jeffrey J. Parker
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/542 , G06F2209/543
摘要： Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel.
摘要翻译：响应于包括创建线程的中断执行应用程序函数调用; 接收具有中断类型的中断; 确定信号量的值是否表示中断被禁用; 如果信号量的值表示中断未被禁用：根据中断的中断类型，线程调用一个或多个预配置函数; 产生线程; 并且如果信号量的值表示中断被禁用：将信号量的值表示为中断的内核是硬禁用的; 并在内核上进行硬禁止中断。

7. 发明申请

US20100088705A1 Call Stack Protection 失效
标题翻译：呼叫堆栈保护
公开(公告)号：US20100088705A1
公开(公告)日：2010-04-08
申请号：US12247497
申请日：2008-10-08
申请人： John E. Attinella , Mark E. Giampapa , Thomas M. Gooding
发明人： John E. Attinella , Mark E. Giampapa , Thomas M. Gooding
IPC分类号： G06F12/02 , G06F9/46
CPC分类号： G06F12/1441
摘要： Call stack protection, including executing at least one application program on the one or more computer processors, including initializing threads of execution, each thread having a call stack, each call stack characterized by a separate guard area defining a maximum extent of the call stack, dispatching one of the threads of the process, including loading a guard area specification for the dispatched thread's call stack guard area from thread context storage into address comparison registers of a processor; determining by use of address comparison logic in dependence upon a guard area specification for the dispatched thread whether each access of memory by the dispatched thread is a precluded access of memory in the dispatched thread's call stack's guard area; and effecting by the address comparison logic an address comparison interrupt for each access of memory that is a precluded access of memory in the dispatched thread's guard area.
摘要翻译：调用堆栈保护，包括在一个或多个计算机处理器上执行至少一个应用程序，包括初始化执行线程，每个线程具有调用堆栈，每个调用堆栈的特征在于定义呼叫堆栈的最大范围的单独保护区域，调度进程的一个线程，包括将调度线程的调用堆栈保护区域的保护区域规范从线程上下文存储加载到处理器的地址比较寄存器中; 通过使用地址比较逻辑，根据被调度的线程的保护区域规范来确定被调度线程的每个存储器的访问是否是被调度的线程的调用堆栈的保护区域中的存储器的被阻止的访问; 并且通过地址比较逻辑执行地址比较中断，用于存储器的每次存取，这是存储在调度线程的保护区域中的被阻止的访问。

8. 发明申请

US20090177828A1 Executing Application Function Calls in Response to an Interrupt 有权
标题翻译：执行响应中断的应用程序函数调用
公开(公告)号：US20090177828A1
公开(公告)日：2009-07-09
申请号：US11968720
申请日：2008-01-03
申请人： Gheorghe Almasi , Charles J. Archer , Mark E. Giampapa , Thomas M. Gooding , Philip Heidelberger , Jeffrey J. Parker
发明人： Gheorghe Almasi , Charles J. Archer , Mark E. Giampapa , Thomas M. Gooding , Philip Heidelberger , Jeffrey J. Parker
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F9/542 , G06F2209/543
摘要： Executing application function calls in response to an interrupt including creating a thread; receiving an interrupt having an interrupt type; determining whether a value of a semaphore represents that interrupts are disabled; if the value of the semaphore represents that interrupts are not disabled: calling, by the thread, one or more preconfigured functions in dependence upon the interrupt type of the interrupt; yielding the thread; and if the value of the semaphore represents that interrupts are disabled: setting the value of the semaphore to represent to a kernel that interrupts are hard-disabled; and hard-disabling interrupts at the kernel.
摘要翻译：响应于包括创建线程的中断执行应用程序函数调用; 接收具有中断类型的中断; 确定信号量的值是否表示中断被禁用; 如果信号量的值表示中断未被禁用：根据中断的中断类型，线程调用一个或多个预配置函数; 产生线程; 并且如果信号量的值表示中断被禁用：将信号量的值表示为中断的内核是硬禁用的; 并在内核上进行硬禁止中断。

9. 发明申请

US20090006894A1 METHOD AND APPARATUS TO DEBUG AN INTEGRATED CIRCUIT CHIP VIA SYNCHRONOUS CLOCK STOP AND SCAN 失效
标题翻译：通过同步时钟停止和扫描来调试集成电路芯片的方法和设备
公开(公告)号：US20090006894A1
公开(公告)日：2009-01-01
申请号：US11768791
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Matthew R. Ellavsky , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Lance G. Hehenberger , Martin Ohmacht
发明人： Ralph E. Bellofatto , Matthew R. Ellavsky , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Lance G. Hehenberger , Martin Ohmacht
IPC分类号： G06F11/00
CPC分类号： G06F11/2236
摘要： An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.
摘要翻译：一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

10. 发明申请

US20090006873A1 POWER THROTTLING OF COLLECTIONS OF COMPUTING ELEMENTS 失效
标题翻译：计算元素收集的功率曲线
公开(公告)号：US20090006873A1
公开(公告)日：2009-01-01
申请号：US11768752
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
发明人： Ralph E. Bellofatto , Paul W. Coteus , Paul G. Crumley , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf Haring , Mark G. Megerian , Martin Ohmacht , Don D. Reed , Richard A. Swetz , Todd Takken
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/206
摘要： An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.
摘要翻译：用于控制计算机中的电力使用的装置和方法包括与本地控制装置通信的多个计算机，以及向本地控制装置和计算机供电的电源。多个传感器与计算机通信以确定计算机的功率使用，并且系统控制装置与计算机通信以控制计算机的电力使用。

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