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1. 发明授权

US08452919B2 Advanced memory device having improved performance, reduced power and increased reliability 有权
标题翻译：先进的存储器件具有改进的性能，降低的功率和增加的可靠性
公开(公告)号：US08452919B2
公开(公告)日：2013-05-28
申请号：US13567357
申请日：2012-08-06
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

2. 发明授权

US08358522B2 Synchronous rectifier gate drive timing to compensate for transformer leakage inductance 有权
标题翻译：同步整流栅驱动定时补偿变压器漏电感
公开(公告)号：US08358522B2
公开(公告)日：2013-01-22
申请号：US12836933
申请日：2010-07-15
申请人： Paul W. Coteus , Andrew Ferencz
发明人： Paul W. Coteus , Andrew Ferencz
IPC分类号： H02M5/42
CPC分类号： H02M3/33592 , H02M2001/0048 , Y02B70/1475 , Y02B70/1491
摘要： An apparatus for providing synchronous rectifier gate drive timing is described. The apparatus includes circuitry to receive a first signal. The apparatus also includes circuitry to generate a second signal by modifying the first signal to delay a transition from high to low for a non-zero overlap duration. An output to apply an inverse of the first signal as a gate drive timing of at least a first transistor and to apply the second signal as a gate drive timing of at least a second transistor, where the first transistor is a part of a primary side of a full-bridge synchronous rectifier and the second transistor is a part of a secondary side of the full-bridge synchronous rectifier is also included. The second signal and the inverse of the first signal are high during the overlap duration. Methods and program storage devices are also disclosed.
摘要翻译：描述了一种用于提供同步整流栅驱动定时的装置。该装置包括用于接收第一信号的电路。该装置还包括通过修改第一信号以在非零重叠持续时间内将从高转变为低的过渡来产生第二信号的电路。用于将第一信号的反相作为至少第一晶体管的栅极驱动定时的输出，并施加第二信号作为至少第二晶体管的栅极驱动定时，其中第一晶体管是初级侧的一部分的全桥同步整流器，而第二晶体管也是全桥同步整流二次侧的一部分。第二信号和第一信号的反相在重叠期间是高的。还公开了方法和程序存储装置。

3. 发明授权

US08343804B2 Implementing multiple different types of dies for memory stacking 有权
标题翻译：实现多种不同类型的模具进行内存堆叠
公开(公告)号：US08343804B2
公开(公告)日：2013-01-01
申请号：US13364346
申请日：2012-02-02
申请人： Paul W. Coteus , Kyu-hyoun Kim
发明人： Paul W. Coteus , Kyu-hyoun Kim
IPC分类号： H01L21/00
CPC分类号： H01L24/73 , H01L23/481 , H01L24/06 , H01L24/48 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/06181 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73257 , H01L2225/06541 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01033 , H01L2924/10253 , H01L2924/1434 , H01L2924/15311 , H01L2224/45099 , H01L2924/00
摘要： A method and structure are provided for implementing multiple different types of dies for memory stacking. A common wafer is provided with a predefined reticle type. The reticle type includes a plurality of arrays, and a plurality of periphery segments. A plurality of through-silicon-vias (TSVs) is placed at boundaries between array and periphery segments. Multiple different types of dies for memory stacking are obtained based upon selected scribing of the dies from the common wafer.
摘要翻译：提供了一种用于实现用于存储器堆叠的多种不同类型的管芯的方法和结构。普通晶片具有预定的掩模版类型。标线型包括多个阵列和多个外围段。多个通硅通孔（TSV）被放置在阵列和外围段之间的边界处。基于从公共晶片选择划线的模具，获得用于存储器堆叠的多种不同类型的管芯。

4. 发明申请

US20120266008A1 SYSTEM-WIDE POWER MANAGEMENT CONTROL VIA CLOCK DISTRIBUTION NETWORK 有权
标题翻译：通过时钟分配网络进行系统的电源管理控制
公开(公告)号：US20120266008A1
公开(公告)日：2012-10-18
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/12
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

5. 发明授权

US08278745B2 Through board stacking of multiple LGA-connected components 有权
标题翻译：通过板堆叠多个LGA连接的组件
公开(公告)号：US08278745B2
公开(公告)日：2012-10-02
申请号：US12543104
申请日：2009-08-18
申请人： Paul W. Coteus , Shawn A. Hall , Gareth G. Hougham , Alphonso P. Lanzetta , Rick A. Rand
发明人： Paul W. Coteus , Shawn A. Hall , Gareth G. Hougham , Alphonso P. Lanzetta , Rick A. Rand
IPC分类号： H01L23/52
CPC分类号： H05K3/325 , H05K2201/0314 , H05K2201/10545 , H05K2201/10719 , H05K2201/2018
摘要： A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.
摘要翻译：提供了一种封装设计，其中芯片模块通过PCB顶表面上的焊盘网格阵列（LGA）连接到印刷电路板（PCB），并且电源通过第二个LGA连接到PCB PCB的底面。芯片模块，电源和LGA的堆叠被保持就位并用致动硬件压缩形成可调节的框架。该封装允许模块或PS的现场可替代性，并提供从PS到模块的最短可能布线距离，从而实现更高的性能。

6. 发明授权

US08268389B2 Precast thermal interface adhesive for easy and repeated, separation and remating 有权
标题翻译：预制热界面粘合剂，易于重复，分离和重新配制
公开(公告)号：US08268389B2
公开(公告)日：2012-09-18
申请号：US12684174
申请日：2010-01-08
申请人： Evan G. Colgan , Paul W. Coteus , Michael A. Gaynes , Kenneth C. Marston , Steven P. Ostrander
发明人： Evan G. Colgan , Paul W. Coteus , Michael A. Gaynes , Kenneth C. Marston , Steven P. Ostrander
IPC分类号： B05D5/10
CPC分类号： B32B37/1207 , B32B37/26 , B32B2037/243 , B32B2037/268 , B32B2309/02 , B32B2311/12 , B32B2311/24 , B32B2457/08 , Y10T156/11 , Y10T156/1195 , Y10T428/2804 , Y10T428/2813 , Y10T428/2861
摘要： Precast curable thermal interface adhesives facilitating the easy and repeatable separation and remaining of electronic components at thermal interfaces thereof, and a method for implementing the foregoing repeatable separation and remating at the thermal interfaces of components through the use of such adhesives.
摘要翻译：预制的可固化热界面粘合剂便于在其热界面处容易且可重复地分离和保留电子部件，以及用于通过使用这种粘合剂在组件的热界面处实现上述可重复分离和重新化的方法。

7. 发明授权

US08191245B2 Method of forming a land grid array (LGA) interposer 有权
标题翻译：形成平面阵列（LGA）插入器的方法
公开(公告)号：US08191245B2
公开(公告)日：2012-06-05
申请号：US12116317
申请日：2008-05-07
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R9/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.
摘要翻译：包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。插入件在横截面中具有半环形结构，并由介电弹性体材料构成。多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触飞机还提供了一种制造焊盘栅格阵列中介层结构的方法。

8. 发明申请

US20110171466A1 PRECAST THERMAL INTERFACE ADHESIVE FOR EASY AND REPEATED, SEPARATION AND REMATING 有权
标题翻译：预热接口粘合剂用于轻松和重复，分离和除尘
公开(公告)号：US20110171466A1
公开(公告)日：2011-07-14
申请号：US12684174
申请日：2010-01-08
申请人： Evan George Colgan , Paul W. Coteus , Michael Authony Gaynes , Kenneth Charles Marston , Steven P. Ostrander
发明人： Evan George Colgan , Paul W. Coteus , Michael Authony Gaynes , Kenneth Charles Marston , Steven P. Ostrander
IPC分类号： B32B7/06 , B32B38/10
CPC分类号： B32B37/1207 , B32B37/26 , B32B2037/243 , B32B2037/268 , B32B2309/02 , B32B2311/12 , B32B2311/24 , B32B2457/08 , Y10T156/11 , Y10T156/1195 , Y10T428/2804 , Y10T428/2813 , Y10T428/2861
摘要： Precast curable thermal interface adhesives facilitating the easy and repeatable separation and remaining of electronic components at thermal interfaces thereof, and a method for implementing the foregoing repeatable separation and remating at the thermal interfaces of components through the use of such adhesives.
摘要翻译：预制的可固化热界面粘合剂便于在其热界面处容易且可重复地分离和保留电子部件，以及用于通过使用这种粘合剂在组件的热界面处实现上述可重复分离和重新化的方法。

9. 发明申请

US20110072219A1 MANAGING COHERENCE VIA PUT/GET WINDOWS 失效
标题翻译：通过输入/获取窗口管理相关性
公开(公告)号：US20110072219A1
公开(公告)日：2011-03-24
申请号：US12953770
申请日：2010-11-24
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Phillip Heidelberger , Dirk Hoenicke , Martin Ohmacht
IPC分类号： G06F12/08
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： A method and apparatus for managing coherence between two processors of a two processor node of a multi-processor computer system. Generally the present invention relates to a software algorithm that simplifies and significantly speeds the management of cache coherence in a message passing parallel computer, and to hardware apparatus that assists this cache coherence algorithm. The software algorithm uses the opening and closing of put/get windows to coordinate the activated required to achieve cache coherence. The hardware apparatus may be an extension to the hardware address decode, that creates, in the physical memory address space of the node, an area of virtual memory that (a) does not actually exist, and (b) is therefore able to respond instantly to read and write requests from the processing elements.
摘要翻译：一种用于管理多处理器计算机系统的两个处理器节点的两个处理器之间的相干性的方法和装置。通常，本发明涉及一种软件算法，其简化并显着加速了传送并行计算机的消息中的高速缓存一致性的管理以及辅助该高速缓存一致性算法的硬件设备。软件算法使用put / get窗口的打开和关闭来协调激活的所需要的，以实现缓存一致性。硬件设备可以是硬件地址解码的扩展，其在节点的物理存储器地址空间中创建（a）实际不存在的虚拟存储器的区域，并且（b）因此能够立即响应从处理元素读取和写入请求。

10. 发明申请

US20110055671A1 ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY 有权
标题翻译：具有改进性能，降低功耗和提高可靠性的高级存储设备
公开(公告)号：US20110055671A1
公开(公告)日：2011-03-03
申请号：US12553400
申请日：2009-09-03
申请人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
发明人： Kyu-Hyoun Kim , George L. Chiu , Paul W. Coteus , Daniel M. Dreps , Kevin C. Gower , Hillery C. Hunter , Charles A. Kilmer , Warren E. Maule
IPC分类号： G11C7/00 , G11C8/18 , H03M13/09 , G06F11/07 , G06F11/10
CPC分类号： G11C7/1078 , G06F11/1028 , G11C7/04 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/401 , G11C11/406 , G11C11/40611 , G11C11/40615 , G11C11/40626 , G11C11/4076 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device.
摘要翻译：具有改进性能，降低功耗和增加可靠性的高级内存。存储器件包括存储器阵列，用于接收命令和相关联的数据的接收器，用于对接收到的命令执行错误控制检查的差错控制编码电路以及用于防止相关联的数据被响应地写入存储器阵列的数据屏蔽电路对错误控制编码电路检测接收到的命令中的错误。另一个存储器件包括可编程序序。另一存储器件包括快速退出自刷新模式。另一种存储装置包括由特征装置控制的自动刷新功能。另一存储器件包括由存储器件的特性控制的自动刷新功能。

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