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1. 发明授权

US06808462B2 Training shoe for soccer 失效
标题翻译：足球训练鞋
公开(公告)号：US06808462B2
公开(公告)日：2004-10-26
申请号：US10179501
申请日：2002-06-25
申请人： Gregory P. Snyder , Matthew R. Ellavsky , Richard S. Little , Michael Nordquist
发明人： Gregory P. Snyder , Matthew R. Ellavsky , Richard S. Little , Michael Nordquist
IPC分类号： A63B6900
CPC分类号： G09B19/0038 , A43B3/00 , A43B3/0005 , A43B3/0021 , A43B5/02 , A63B69/002 , A63B2071/0625 , A63B2071/0627
摘要： A training shoe for soccer includes a pressure-responsive sensor mounted with respect to a soccer shoe at a selected location, for example at the instep or along the laces at the top of the shoe. When a soccer ball is kicked at the selected location, the sensor provides an electrical signal to a microprocessor, causing selection logic in the microprocessor to choose one of several control words. The selected control word is provided to a voice playback circuit to select one of several digital data sets, each set corresponding to a different sound. The playback circuit provides an analog electrical control signal to a speaker, thereby generating a selected sound corresponding to the selected digital data set. System components can be mounted permanently to a shoe, or to a cover or strap arrangement releasably mounted to the shoe.
摘要翻译：用于足球的训练鞋包括在选定位置处相对于足球鞋安装的压力响应传感器，例如在脚背或鞋的顶部的鞋带。当足球在所选择的位置踢球时，传感器向微处理器提供电信号，使得微处理器中的选择逻辑选择几个控制字中的一个。所选择的控制字被提供给语音重放电路，以选择对应于不同声音的多个数字数据集中的一个。播放电路向扬声器提供模拟电气控制信号，从而产生对应于所选择的数字数据集的选定声音。系统部件可以永久地安装在鞋子上，或者可拆卸地安装在鞋子上的盖子或带子装置上。

2. 发明申请

US20130042214A1 IIMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT 失效
标题翻译：取消Z方向广域网端口分配
公开(公告)号：US20130042214A1
公开(公告)日：2013-02-14
申请号：US13208046
申请日：2011-08-11
申请人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
发明人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
IPC分类号： G06F9/45
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/66
摘要： A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现用于异构分层集成电路芯片的随机逻辑宏的增强的Z方向宏端口分配或三维端口创建。在宏的层上提供初始端口布局。初始端口放置被扩展以提供包括沿z轴的多个金属层的三维端口形状。在扩展的三维端口形状内定义每个宏级和芯片顶级的布线。扩大的三维端口形状的每个不必要的金属层被去除，提供最终的三维端口形状。

3. 发明申请

US20090241073A1 Radiation Tolerance by Clock Signal Interleaving 失效
标题翻译：通过时钟信号交错的辐射公差
公开(公告)号：US20090241073A1
公开(公告)日：2009-09-24
申请号：US12051002
申请日：2008-03-19
申请人： Matthew R. Ellavsky , Aj KleinOsowski , Scott M. Willenborg
发明人： Matthew R. Ellavsky , Aj KleinOsowski , Scott M. Willenborg
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/62
摘要： A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.
摘要翻译：一种设计集成电路的方法使用时钟信号交织来减少由时钟分配网络中的不适引起的软错误的可能性。电路描述中的至少两个电路被识别为对辐射敏感，并且不同的时钟分配节点被分配给两个电路。公开了几个示例性实现。第二电路可以是第一电路的冗余复制品，例如复位电路。第一和第二电路可以是模块化冗余电路的组件，例如三模块冗余触发器。第一电路可以包括用于诸如寄存器或存储器阵列的存储阵列的入口的一组数据位，并且第二电路可以包括与该条目相关联的一组校验位。

4. 发明授权

US08448121B2 Implementing Z directional macro port assignment 失效
标题翻译：实现Z方向宏端口分配
公开(公告)号：US08448121B2
公开(公告)日：2013-05-21
申请号：US13208046
申请日：2011-08-11
申请人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
发明人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5077 , G06F2217/66
摘要： A method, system and computer program product are provided for implementing an enhanced Z-directional macro port assignment or three-dimensional port creation for random logic macros of heterogeneous hierarchical integrated circuit chips. An initial port placement is provided on a layer for a macro. The initial port placement is expanded to provide a three-dimensional port shape including a plurality of metal layers along a z-axis. Wire routing of each of the macro level and a chip top level is defined within the expanded three-dimensional port shape. Each unnecessary metal layer of the expanded three-dimensional port shape is removed, providing a final three-dimensional port shape.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于实现用于异构分层集成电路芯片的随机逻辑宏的增强的Z方向宏端口分配或三维端口创建。在宏的层上提供初始端口布局。初始端口放置被扩展以提供包括沿z轴的多个金属层的三维端口形状。在扩展的三维端口形状内定义每个宏级和芯片顶级的布线。扩大的三维端口形状的每个不必要的金属层被去除，提供最终的三维端口形状。

5. 发明申请

US20110219208A1 MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER 有权
标题翻译：多层高效平行超级计算机
公开(公告)号：US20110219208A1
公开(公告)日：2011-09-08
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

6. 发明申请

US20110119475A1 GLOBAL SYNCHRONIZATION OF PARALLEL PROCESSORS USING CLOCK PULSE WIDTH MODULATION 有权
标题翻译：使用时钟脉冲宽度调制的并行处理器的全局同步
公开(公告)号：US20110119475A1
公开(公告)日：2011-05-19
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/12 , G06F1/10 , G06F9/00 , G06F1/08
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

7. 发明授权

US08412974B2 Global synchronization of parallel processors using clock pulse width modulation 有权
标题翻译：使用时钟脉宽调制的并行处理器的全局同步
公开(公告)号：US08412974B2
公开(公告)日：2013-04-02
申请号：US12696764
申请日：2010-01-29
申请人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
发明人： Dong Chen , Matthew R. Ellavsky , Ross L. Franke , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Mark J. Jeanson , Gerard V. Kopcsay , Thomas A. Liebsch , Daniel Littrell , Martin Ohmacht , Don D. Reed , Brandon E. Schenck , Richard A. Swetz
IPC分类号： G06F1/04 , G06F1/12 , G06F15/16
CPC分类号： G06F1/08 , G06F1/10
摘要： A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
摘要翻译：电路产生具有脉冲宽度修改的全局时钟信号，以使并行计算系统中的处理器同步。电路可以包括硬件模块和时钟分离器。硬件模块可以产生时钟信号并对时钟信号进行脉冲宽度修改。脉冲宽度修改在时钟信号的时钟周期内改变脉冲宽度。时钟分配器可以将脉冲宽度修改的时钟信号分配给并行计算系统中的多个处理器。

8. 发明申请

US20120290995A1 CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST 失效
标题翻译：更改缓存器在网络列表中的位置
公开(公告)号：US20120290995A1
公开(公告)日：2012-11-15
申请号：US13106005
申请日：2011-05-12
申请人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
发明人： Matthew R. Ellavsky , Sean T. Evans , Timothy D. Helvey , Phillip P. Normand , Jason L. Van Vreede , Bradley C. White
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/505 , G06F17/5068
摘要： In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location.
摘要翻译：在一个实施例中，缓冲器托架由可移动对象表示，该可移动对象在网表中具有单位内的位置。表示缓冲区的可移动对象的位置将更改为网络列表中的新位置，如果更改位置可改善单元中的位置。在一个实施例中，在确定是否将位置改变到新位置时，考虑将可移动物体连接到人造针的网的净重。在一个实施例中，在确定是否将位置改变到新位置时考虑包围该位置的边界区域。

9. 发明授权

US08140925B2 Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan 失效
标题翻译：通过同步时钟停止和扫描来调试集成电路芯片的方法和装置
公开(公告)号：US08140925B2
公开(公告)日：2012-03-20
申请号：US11768791
申请日：2007-06-26
申请人： Ralph E. Bellofatto , Matthew R. Ellavsky , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Lance G. Hehenberger , Martin Ohmacht
发明人： Ralph E. Bellofatto , Matthew R. Ellavsky , Alan G. Gara , Mark E. Giampapa , Thomas M. Gooding , Rudolf A. Haring , Lance G. Hehenberger , Martin Ohmacht
IPC分类号： G01R31/28 , G06F1/12
CPC分类号： G06F11/2236
摘要： An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.
摘要翻译：一种用于评估电子或集成电路（IC）的状态的装置和方法，每个IC包括用于控制IC子单元的操作的一个或多个处理器元件，以及每个支持多个时钟域的IC。该方法包括：根据确定的定时配置，产生与一个或多个IC子单元相对应的用于开始一个或多个IC子单元的操作的同步的使能信号组; 计数，响应于同步的一组使能信号的一个信号，多个主处理器IC时钟周期; 并且在获得期望的时钟周期数时，产生用于每个唯一频率时钟域的停止信号以同步地停止每个相应频率时钟域的功能时钟; 并且在确定性地同时停止所有频率时钟域上的所有片上功能时钟时，以期望的IC芯片状态扫描数据值。该装置和方法使得能够使用片上电路和软件的组合来构建运行中的IC芯片的状态的任何部分的逐周期视图。

10. 发明授权

US09081501B2 Multi-petascale highly efficient parallel supercomputer 有权
标题翻译：多千兆高效并行超级计算机
公开(公告)号：US09081501B2
公开(公告)日：2015-07-14
申请号：US13004007
申请日：2011-01-10
申请人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
发明人： Sameh Asaad , Ralph E. Bellofatto , Michael A. Blocksome , Matthias A. Blumrich , Peter Boyle , Jose R. Brunheroto , Dong Chen , Chen-Yong Cher , George L. Chiu , Norman Christ , Paul W. Coteus , Kristan D. Davis , Gabor J. Dozsa , Alexandre E. Eichenberger , Noel A. Eisley , Matthew R. Ellavsky , Kahn C. Evans , Bruce M. Fleischer , Thomas W. Fox , Alan Gara , Mark E. Giampapa , Thomas M. Gooding , Michael K. Gschwind , John A. Gunnels , Shawn A. Hall , Rudolf A. Haring , Philip Heidelberger , Todd A. Inglett , Brant L. Knudson , Gerard V. Kopcsay , Sameer Kumar , Amith R. Mamidala , James A. Marcella , Mark G. Megerian , Douglas R. Miller , Samuel J. Miller , Adam J. Muff , Michael B. Mundy , John K. O'Brien , Kathryn M. O'Brien , Martin Ohmacht , Jeffrey J. Parker , Ruth J. Poole , Joseph D. Ratterman , Valentina Salapura , David L. Satterfield , Robert M. Senger , Brian Smith , Burkhard Steinmacher-Burow , William M. Stockdell , Craig B. Stunkel , Krishnan Sugavanam , Yutaka Sugawara , Todd E. Takken , Barry M. Trager , James L. Van Oosten , Charles D. Wait , Robert E. Walkup , Alfred T. Watson , Robert W. Wisniewski , Peng Wu
IPC分类号： G06F15/173 , G06F9/06 , G06F15/76
CPC分类号： G06F13/287 , G06F9/06 , G06F9/3004 , G06F9/30047 , G06F9/3885 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/0864 , G06F12/1027 , G06F15/17381 , G06F15/17387 , G06F15/76 , G06F15/8069 , G06F2212/1016 , G06F2212/602 , G06F2212/6022 , G06F2212/6024 , G06F2212/6032 , Y02D10/13 , Y02D10/14
摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.
摘要翻译：具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。

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