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1. 发明授权

US08577950B2 Matrix multiplication operations with data pre-conditioning in a high performance computing architecture 失效
标题翻译：在高性能计算架构中使用数据预处理的矩阵乘法运算
公开(公告)号：US08577950B2
公开(公告)日：2013-11-05
申请号：US12542255
申请日：2009-08-17
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
IPC分类号： G06F7/52
CPC分类号： G06F17/16 , G06F9/30014 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30072 , G06F9/30094 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： Mechanisms for performing matrix multiplication operations with data pre-conditioning in a high performance computing architecture are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A load and splat operation is performed to load an element of a second vector operand and replicating the element to each of a plurality of elements of a second target vector register. A multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product of the matrix multiplication operation is accumulated with other partial products of the matrix multiplication operation.
摘要翻译：提供了用于在高性能计算架构中执行数据预处理的矩阵乘法运算的机制。执行向量加载操作以将矩阵乘法运算的第一向量操作数加载到第一目标向量寄存器。执行加载和拼接操作以加载第二向量操作数的元素并将元素复制到第二目标向量寄存器的多个元素中的每一个。对第一目标向量寄存器的元素和第二目标向量寄存器的元素执行乘法加法运算，以生成矩阵乘法运算的部分乘积。矩阵乘法运算的部分乘积与矩阵乘法运算的其他部分积积累。

2. 发明申请

US20120290816A1 Optimized Scalar Promotion with Load and Splat SIMD Instructions 失效
标题翻译：通过加载和Splat SIMD指令优化标量升级
公开(公告)号：US20120290816A1
公开(公告)日：2012-11-15
申请号：US13555435
申请日：2012-07-23
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
IPC分类号： G06F9/30
CPC分类号： G06F8/45
摘要： Mechanisms for optimizing scalar code executed on a single instruction multiple data (SIMD) engine are provided. Placement of vector operation-splat operations may be determined based on an identification of scalar and SIMD operations in an original code representation. The original code representation may be modified to insert the vector operation-splat operations based on the determined placement of vector operation-splat operations to generate a first modified code representation. Placement of separate splat operations may be determined based on identification of scalar and SIMD operations in the first modified code representation. The first modified code representation may be modified to insert or delete separate splat operations based on the determined placement of the separate splat operations to generate a second modified code representation. SIMD code may be output based on the second modified code representation for execution by the SIMD engine.
摘要翻译：提供了在单指令多数据（SIMD）引擎上执行的优化标量代码的机制。可以基于原始代码表示中的标量和SIMD操作的标识来确定矢量操作 - 拼接操作的放置。可以修改原始代码表示以基于所确定的向量操作 - 分组操作的放置来插入向量操作 - 拼接操作以生成第一修改代码表示。可以基于第一修改代码表示中的标量和SIMD操作的标识来确定单独的拼接操作的放置。可以修改第一修改代码表示以基于确定的单独splat操作的布局来插入或删除单独的splat操作以生成第二修改代码表示。可以基于SIMD引擎执行的第二修改代码表示来输出SIMD代码。

3. 发明申请

US20120011348A1 Matrix Multiplication Operations Using Pair-Wise Load and Splat Operations 有权
标题翻译：使用配对加载和Splat操作的矩阵乘法运算
公开(公告)号：US20120011348A1
公开(公告)日：2012-01-12
申请号：US12834464
申请日：2010-07-12
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , Valentina Salapura
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels , Valentina Salapura
IPC分类号： G06F9/302
CPC分类号： G06F9/30043 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： Mechanisms for performing a matrix multiplication operation are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A pair-wise load and splat operation is performed to load a pair of scalar values of a second vector operand and replicate the pair of scalar values within a second target vector register. An operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product is accumulated with other partial products and a resulting accumulated partial product is stored. This operation may be repeated for a second pair of scalar values of the second vector operand.
摘要翻译：提供了执行矩阵乘法运算的机构。执行向量加载操作以将矩阵乘法运算的第一向量操作数加载到第一目标向量寄存器。执行成对的加载和拼接操作以加载第二向量操作数的一对标量值，并在第二目标向量寄存器内复制一对标量值。对第一目标向量寄存器的元素和第二目标向量寄存器的元素执行操作，以生成矩阵乘法运算的部分乘积。部分产品与其他部分产品一起积累，并存储所得累积的部分产品。对于第二向量操作数的第二对标量值可以重复该操作。

4. 发明授权

US08055878B2 Method and structure for skewed block-cyclic distribution of lower-dimensional data arrays in higher-dimensional processor grids 失效
标题翻译：低维数据阵列在高维处理器网格中的偏态块循环分布的方法和结构
公开(公告)号：US08055878B2
公开(公告)日：2011-11-08
申请号：US11052216
申请日：2005-02-08
申请人： Siddhartha Chatterjee , John A. Gunnels
发明人： Siddhartha Chatterjee , John A. Gunnels
IPC分类号： G06F15/00
CPC分类号： G06F15/8007
摘要： A method and structure of distributing elements of an array of data in a computer memory to a specific processor of a multi-dimensional mesh of parallel processors includes designating a distribution of elements of at least a portion of the array to be executed by specific processors in the multi-dimensional mesh of parallel processors. The pattern of the designating includes a cyclical repetitive pattern of the parallel processor mesh, as modified to have a skew in at least one dimension so that both a row of data in the array and a column of data in the array map to respective contiguous groupings of the processors such that a dimension of the contiguous groupings is greater than one.
摘要翻译：将计算机存储器中的数据阵列的元素分配到并行处理器的多维网格的特定处理器的方法和结构包括指定由特定处理器执行的阵列的至少一部分的分布，并行处理器的多维网格。指定的模式包括并行处理器网格的循环重复模式，被修改为在至少一个维度上具有偏斜，使得阵列中的一行数据和阵列中的数据列映射到相应的连续分组的处理器，使得连续分组的维数大于1。

5. 发明申请

US20110040821A1 Matrix Multiplication Operations with Data Pre-Conditioning in a High Performance Computing Architecture 失效
标题翻译：在高性能计算架构中使用数据预处理的矩阵乘法运算
公开(公告)号：US20110040821A1
公开(公告)日：2011-02-17
申请号：US12542255
申请日：2009-08-17
申请人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
发明人： Alexandre E. Eichenberger , Michael K. Gschwind , John A. Gunnels
IPC分类号： G06F17/16 , G06F7/52
CPC分类号： G06F17/16 , G06F9/30014 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30043 , G06F9/30072 , G06F9/30094 , G06F9/30109 , G06F9/3013 , G06F9/3885 , G06F9/3887
摘要： Mechanisms for performing matrix multiplication operations with data pre-conditioning in a high performance computing architecture are provided. A vector load operation is performed to load a first vector operand of the matrix multiplication operation to a first target vector register. A load and splat operation is performed to load an element of a second vector operand and replicating the element to each of a plurality of elements of a second target vector register. A multiply add operation is performed on elements of the first target vector register and elements of the second target vector register to generate a partial product of the matrix multiplication operation. The partial product of the matrix multiplication operation is accumulated with other partial products of the matrix multiplication operation.
摘要翻译：提供了用于在高性能计算架构中执行数据预处理的矩阵乘法运算的机制。执行向量加载操作以将矩阵乘法运算的第一向量操作数加载到第一目标向量寄存器。执行加载和拼接操作以加载第二向量操作数的元素并将元素复制到第二目标向量寄存器的多个元素中的每一个。对第一目标向量寄存器的元素和第二目标向量寄存器的元素执行乘法加法运算，以生成矩阵乘法运算的部分乘积。矩阵乘法运算的部分乘积与矩阵乘法运算的其他部分积积累。

6. 发明申请

US20090292758A1 Optimized Corner Turns for Local Storage and Bandwidth Reduction 有权
标题翻译：优化的角落转向本地存储和带宽减少
公开(公告)号：US20090292758A1
公开(公告)日：2009-11-26
申请号：US12125996
申请日：2008-05-23
申请人： Daniel A. Brokenshire , John A. Gunnels , Michael D. Kistler
发明人： Daniel A. Brokenshire , John A. Gunnels , Michael D. Kistler
IPC分类号： G06F7/52 , G06F12/02
CPC分类号： G06F17/16
摘要： A block matrix multiplication mechanism is provided for reversing the visitation order of blocks at corner turns when performing a block matrix multiplication operation in a data processing system. By reversing the visitation order, the mechanism eliminates a block load at the corner turns. In accordance with the illustrative embodiment, a corner return is referred to as a “bounce” corner turn and results in a serpentine patterned processing order of the matrix blocks. The mechanism allows the data processing system to perform a block matrix multiplication operation with a maximum of three block transfers per time step. Therefore, the mechanism reduces maximum throughput and increases performance. In addition, the mechanism also reduces the number of multi-buffered local store buffers.
摘要翻译：提供了一种块矩阵乘法机制，用于在数据处理系统中执行块矩阵乘法运算时，使拐角处的块的访问次序反转。通过反转巡视顺序，该机构消除了拐角处的挡块负载。根据说明性实施例，角返回被称为“反弹”转弯，并且导致矩阵块的蛇形图案化处理顺序。该机制允许数据处理系统执行块矩阵乘法运算，每个时间步长最多有三个块传输。因此，该机制降低了最大吞吐量并提高了性能。此外，该机制还减少了多缓冲本地存储缓冲区的数量。

7. 发明申请

US20090063607A1 METHOD AND STRUCTURE FOR FAST IN-PLACE TRANSFORMATION OF STANDARD FULL AND PACKED MATRIX DATA FORMATS 有权
标题翻译：标准完整和包装矩阵数据格式的快速插入转换的方法和结构
公开(公告)号：US20090063607A1
公开(公告)日：2009-03-05
申请号：US11849272
申请日：2007-09-01
申请人： Fred Gehrung Gustavson , John A. Gunnels , James C. Sexton
发明人： Fred Gehrung Gustavson , John A. Gunnels , James C. Sexton
IPC分类号： G06F7/32
CPC分类号： G06F17/16 , G06F7/78 , G06F12/0207 , G06F2212/454
摘要： A method and structure for an in-place transformation of matrix data. For a matrix A stored in one of a standard full format or a packed format and a transformation T having a compact representation, blocking parameters MB and NB are chosen, based on a cache size. A sub-matrix A1 of A, A1 having size M1=m*MB by N1=n*NB, is worked on, and any of a residual remainder of A is saved in a buffer B. Sub-matrix A1 is worked on by contiguously moving and contiguously transforming A1 in-place into a New Data Structure (NDS), applying the transformation T in units of MB*NB contiguous double words to the NDS format of A1, thereby replacing A1 with the contents of T(A1), and moving and transforming NDS T(A1) to standard data format T(A1) with holes for the remainder of A in buffer B. The contents of buffer B is contiguously copied into the holes of A2, thereby providing in-place transformed matrix T(A).
摘要翻译：矩阵数据的就地转换的方法和结构。对于以标准全格式或打包格式之一存储的矩阵A和具有紧凑表示的变换T，基于高速缓存大小来选择阻塞参数MB和NB。对于具有M1 = m * MB的N1 = n * NB的A的A1的矩阵A1进行加工，并且A的剩余余数中的任一个保存在缓冲器B中。子矩阵A1由将A1原位连续移动并连续地转换为新数据结构（NDS），将以MB * NB连续双字为单位的变换T应用于A1的NDS格式，从而将A1替换为T（A1）的内容，并且将NDS T（A1）移动并变换为具有用于缓冲器B中的剩余部分的空穴的标准数据格式T（A1）。缓冲器B的内容被连续地复制到A2的孔中，从而提供就地变换矩阵T （一个）。

8. 发明申请

US20090052334A1 SYSTEM AND METHOD FOR DETECTING A FAULTY OBJECT IN A SYSTEM 有权
标题翻译：用于检测系统中的故障对象的系统和方法
公开(公告)号：US20090052334A1
公开(公告)日：2009-02-26
申请号：US12256355
申请日：2008-10-22
申请人： John A. Gunnels , Fred Gehrung Gustavson , Robert Daniel Engle
发明人： John A. Gunnels , Fred Gehrung Gustavson , Robert Daniel Engle
IPC分类号： G08C15/00
CPC分类号： G06F11/0751
摘要： A method (and system) for detecting at least one faulty object in a system including a plurality of objects in communication with each other in an n-dimensional architecture, includes probing a first plane of objects in the n-dimensional architecture and probing at least one other plane of objects in the n-dimensional architecture which would result in identifying a faulty object in the system.
摘要翻译：一种用于检测包括在n维体系结构中彼此通信的多个对象的系统中的至少一个故障对象的方法（和系统），包括：探测n维体系结构中的第一对象平面，并至少探测在n维体系结构中的对象的另一个平面，这将导致识别系统中的故障对象。

9. 发明授权

US08527571B2 Method and structure for producing high performance linear algebra routines using composite blocking based on L1 cache size 失效
公开(公告)号：US08527571B2
公开(公告)日：2013-09-03
申请号：US12341718
申请日：2008-12-22
申请人： Fred Gehrung Gustavson , John A. Gunnels
发明人： Fred Gehrung Gustavson , John A. Gunnels
IPC分类号： G06F7/38
CPC分类号： G06F17/16
摘要： A method (and structure) for performing a matrix subroutine, includes storing data for a matrix subroutine call in a computer memory in an increment block size that is based on a cache size.

10. 发明申请

US20090144745A1 Performance Evaluation of Algorithmic Tasks and Dynamic Parameterization on Multi-Core Processing Systems 审中-公开
标题翻译：多核处理系统中算法任务和动态参数化的性能评估
公开(公告)号：US20090144745A1
公开(公告)日：2009-06-04
申请号：US11947185
申请日：2007-11-29
申请人： John A. Gunnels , Shakti Kapoor , Ravi Kothari , Yogish Sabharwal , James C. Sexton
发明人： John A. Gunnels , Shakti Kapoor , Ravi Kothari , Yogish Sabharwal , James C. Sexton
IPC分类号： G06F9/50 , G06F9/44
CPC分类号： G06F11/3404 , G06F11/3428 , G06F11/3433 , G06F11/3447
摘要： Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system.
摘要翻译：用于评估目标多核处理系统上基于DMA的算法任务的性能的装置包括存储器和耦合到存储器的至少一个处理器。处理器是可操作的：输入指定任务的模板，该模板包括指定DMA操作的DMA相关参数和要执行的计算操作; 通过在目标多核处理系统上运行基准测试来评估指定任务的性能，该基准测试用于使用DMA操作生成数据访问模式，并调用由输入模板指定的规定的计算例程; 并提供表示与目标多核处理系统相对应的指定任务的性能度量的基准测试结果。

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