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1. 发明授权

US5357478A Semiconductor integrated circuit device including a plurality of cell array blocks 失效
标题翻译：包括多个单元阵列块的半导体集成电路装置
公开(公告)号：US5357478A
公开(公告)日：1994-10-18
申请号：US767332
申请日：1991-09-30
申请人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
发明人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： H01L21/822 , G11C5/02 , G11C11/401 , H01L27/04 , H01L27/10 , G11C8/00
CPC分类号： G11C5/025
摘要： A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
摘要翻译：在芯片上形成多个子芯片。输入/输出缓冲区布置在多个子芯片周围。每个子芯片包括子芯片控制电路区域和多个存储单元阵列块。每个存储单元阵列块包括存储单元阵列区域，行解码器和控制电路区域，读出放大器区域和输入/输出锁存区域。

2. 发明授权

US5574729A Redundancy circuit for repairing defective bits in semiconductor memory device 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的冗余电路
公开(公告)号：US5574729A
公开(公告)日：1996-11-12
申请号：US338817
申请日：1994-11-10
申请人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
发明人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G06F11/00
CPC分类号： G11C29/848
摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.
摘要翻译：一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。解码器包括i个输出。每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

3. 发明授权

US5323348A Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit 失效
标题翻译：具有多个存储器阵列并且包括用于修复故障位的冗余电路的半导体存储器件
公开(公告)号：US5323348A
公开(公告)日：1994-06-21
申请号：US767316
申请日：1991-09-30
申请人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
发明人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848
摘要： Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
摘要翻译：公开了用于修复其中存在两列不良存储器单元的DRAM的列修复电路7a，7b。开关元件或电路51-5n，61-6n，71-7（n + 1），81-8（n + 1）的连接状态通过适当地断开分别设置在电路7a， 7b。因此，存储器阵列块891a，891b中的列选择线Y2a和Y（n + 1）b未被激活。两个修复电路7a，7b在半导体衬底上彼此间隔开设置，从而防止了熔丝元件和开关元件或电路的过度集中。

4. 发明授权

US5204837A Semiconductor memory device having test mode 失效
标题翻译：具有测试模式的半导体存储器件
公开(公告)号：US5204837A
公开(公告)日：1993-04-20
申请号：US744750
申请日：1991-08-14
申请人： Makoto Suwa , Hiroshi Miyamoto
发明人： Makoto Suwa , Hiroshi Miyamoto
IPC分类号： G11C29/00 , G11C11/401 , G11C29/14 , G11C29/46 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： G11C29/46
摘要： A DRAM includes a test mode controller generating a test mode designating signal designating a test mode at a fall of an external control signal RAS when the logical levels of external control signals CAS and WE are low, and a power-on reset circuit responsive to a power supply for generating a reset pulse for resetting main circuits for data reading and data writing. Each of the external control signals CAS and WE are supplied to the test mode controller and the main circuits through a buffer circuit. A first buffer circuit for supplying the external control signal RAS to the test mode controller is provided separately from a second buffer circuit for supplying the external control signal RAS to the main circuits. The second buffer circuit receives the output of the power-on reset circuit and the external control signal RAS to buffer the control signal RAS only when no reset pulse is generated. The first buffer circuit receives only the external control signal RAS to continuously buffer the same without being affected by a reset pulse.
摘要翻译： DRAM包括一个测试模式控制器，当外部控制信号＆upbar＆C和＆amp; upbar＆W的逻辑电平为低电平时，产生一个测试模式指定信号，在外部控制信号和上升沿和下拉沿指定测试模式;以及上电复位电路响应于电源产生用于复位用于数据读取和数据写入的主电路的复位脉冲。每个外部控制信号＆upbar＆C和＆amp; upbar＆W通过缓冲电路提供给测试模式控制器和主电路。与外部控制信号和上行＆R连接到主电路的第二缓冲电路分开设置用于将外部控制信号和上行＆amp; R提供给测试模式控制器的第一缓冲电路。第二个缓冲电路接收上电复位电路的输出和外部控制信号和上拉和下拉，只有在没有产生复位脉冲时才缓冲控制信号和上拉电阻＆R。第一个缓冲电路仅接收外部控制信号＆上拉和下拉以连续缓冲，而不受复位脉冲的影响。

5. 发明授权

US5384784A Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
标题翻译：半导体存储器件，包括测试电路及其操作方法
公开(公告)号：US5384784A
公开(公告)日：1995-01-24
申请号：US750040
申请日：1991-08-27
申请人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
发明人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
IPC分类号： G11C11/409 , G11C11/401 , G11C29/00 , G11C29/34 , G06F15/20
CPC分类号： G11C29/34
摘要： A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.
摘要翻译：半导体存储器件包括存储器阵列。存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。第一放大器连接到每个位线对。对应于第一组，写总线读总线和读/测电路。对应于第二组，写总线读总线和读/测电路。列解码器在测试时同时选择多个位线对。在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

6. 发明授权

US5157630A Semiconductor memory which can be prevented from shifting to undesired operation mode 失效
标题翻译：半导体存储器，可以防止发生转换为未经操作的模式
公开(公告)号：US5157630A
公开(公告)日：1992-10-20
申请号：US629727
申请日：1990-12-21
申请人： Makoto Suwa , Hiroshi Miyamoto
发明人： Makoto Suwa , Hiroshi Miyamoto
IPC分类号： G11C11/401 , G11C8/18 , G11C29/00 , G11C29/46 , G11C29/50
CPC分类号： G11C29/46 , G11C8/18
摘要： Disclosed are an RAS input circuit (100a) and a CAS input circuit (200a) applicable to a dynamic random access memory (DRAM). The threshold voltage V.sub.TRAS of the RAS input circuit and the threshold voltage V.sub.TCAS of the CAS input circuit are settled to satisfy the relation V.sub.TRAS >V.sub.TCAS. Therefore, a L level of an external RAS signal is more easily determined by a L level of an external CAS signal. As a result, the DRAM is prevented from erroneously starting its operation under a test mode without an external request.
摘要翻译：公开了适用于动态随机存取存储器（DRAM）的＆amp;＆amp;＆amp;＆amp;＆quot;输入电路（100a）和＆amp; upbar＆C输入电路（200a）。＆upbar＆R输入电路的阈值电压VTRAS和＆upbar＆C输入电路的阈值电压VTCAS得到满足VTRAS> VTCAS的关系。因此，外部＆upbar＆R信号的L电平更容易由外部＆upbar＆C信号的L电平确定。结果，防止DRAM在没有外部请求的情况下在测试模式下错误地开始其操作。

7. 发明授权

US5079743A Circuit for applying selected voltages to dynamic random access memory 失效
标题翻译：将动作选择电压应用于动态随机存取存储器的电路
公开(公告)号：US5079743A
公开(公告)日：1992-01-07
申请号：US436587
申请日：1989-11-15
申请人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
发明人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C29/50008 , G11C29/50 , G11C11/401
摘要： A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The switching circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.
摘要翻译：动态随机存取存储器（DRAM）包括用于选择用于老化的电压的选择电路。开关电路响应于外部控制信号而工作。当选择源电压（Vcc）时，经由电路73和传输栅极将电压（Vcc）提供给存储单元的一个电极，同时通过位线将地电位（Vss）提供给另一电极，一个晶体管。相反，当选择接地电位（Vss）时，在两个电极之间施加反向电压。以这种方式，可以在老化期间更可靠地检查插入在两个电极之间的绝缘体的绝缘性。

8. 发明授权

US5337272A Circuit for applying selected voltages to dynamic random access memory 失效
标题翻译：将选定电压应用于动态随机存取存储器有效老化和存储单元测试的电路
公开(公告)号：US5337272A
公开(公告)日：1994-08-09
申请号：US32554
申请日：1993-03-17
申请人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
发明人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , G11C11/40 , G11C11/407
CPC分类号： G11C29/50008 , G11C29/50 , G11C11/401
摘要： A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The selection circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.
摘要翻译：动态随机存取存储器（DRAM）包括用于选择用于老化的电压的选择电路。选择电路响应于外部控制信号而工作。当选择源电压（Vcc）时，经由电路73和传输栅极将电压（Vcc）提供给存储单元的一个电极，同时通过位线将地电位（Vss）提供给另一电极，一个晶体管。相反，当选择接地电位（Vss）时，在两个电极之间施加反向电压。以这种方式，可以在老化期间更可靠地检查插入在两个电极之间的绝缘体的绝缘性。

9. 发明授权

US5321654A Semiconductor device having no through current flow in standby period 失效
标题翻译：半导体器件在待机期间没有通过电流流动
公开(公告)号：US5321654A
公开(公告)日：1994-06-14
申请号：US863975
申请日：1992-04-06
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： G11C11/408 , G11C5/14 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C7/22 , G11C5/14 , G11C8/18
摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.
摘要翻译：一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

10. 发明授权

US06724223B2 Semiconductor device used in two systems having different power supply voltages 有权
标题翻译：在具有不同电源电压的两个系统中使用的半导体器件
公开(公告)号：US06724223B2
公开(公告)日：2004-04-20
申请号：US10287643
申请日：2002-11-05
申请人： Tetsuichiro Ichiguchi , Tsutomu Nagasawa , Tadaaki Yamauchi , Zengcheng Tian , Makoto Suwa , Junko Matsumoto , Takeo Okamoto , Hideki Yonetani
发明人： Tetsuichiro Ichiguchi , Tsutomu Nagasawa , Tadaaki Yamauchi , Zengcheng Tian , Makoto Suwa , Junko Matsumoto , Takeo Okamoto , Hideki Yonetani
IPC分类号： H03K190175
CPC分类号： G11C7/225 , G11C5/14 , G11C7/22 , G11C11/4074 , G11C11/4076 , H01L27/0255
摘要： A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.
摘要翻译： DRAM的时钟缓冲器包括：第一NAND门，其由第一内部电源电压（2.5V）驱动，并且如果DRAM用于TTL系统接口，则确定输入时钟信号的电平（MLV = 2.5 V）; 以及第二NAND门，其由第二内部电源电压（1.8V）驱动，并且如果DRAM用于1.8V系统接口（MLV = 0V），则确定输入时钟信号的电平。因此，在第一和第二NAND门的每一个中，四个MOS晶体管的尺寸可以分别被设定为最佳值。

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