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1. 发明授权

US06893171B2 Substrate treating apparatus 有权
标题翻译：底物处理装置
公开(公告)号：US06893171B2
公开(公告)日：2005-05-17
申请号：US10417460
申请日：2003-04-16
申请人： Yoshiteru Fukutomi , Kenji Sugimoto , Takashi Ito , Takeo Okamoto , Yukihiko Inagaki , Katsushi Yoshioka , Tsuyoshi Mitsuhashi
发明人： Yoshiteru Fukutomi , Kenji Sugimoto , Takashi Ito , Takeo Okamoto , Yukihiko Inagaki , Katsushi Yoshioka , Tsuyoshi Mitsuhashi
IPC分类号： G03F7/30 , B05C9/14 , B05C13/00 , B65G1/00 , H01L21/00 , H01L21/027 , H01L21/67 , H01L21/677 , G03D5/00 , B65G49/07 , B65H1/00 , G03B27/32
CPC分类号： H01L21/67173 , H01L21/67178 , H01L21/67225 , H01L21/67276 , H01L21/67778 , Y10S414/135
摘要： A substrate treating apparatus disclosed herein realizes improved throughput. The substrate treating apparatus according to this invention includes an antireflection film forming block, a resist film forming block and a developing block arranged in juxtaposition. Each block includes chemical treating modules, heat-treating modules and a single main transport mechanism. The main transport mechanism transports substrates within each block. Transfer of the substrates between adjacent blocks is carried out through substrate rests. The main transport mechanism of each block is not affected by movement of the main transport mechanisms of the adjoining blocks. Consequently, the substrates may be transported efficiently to improve the throughput of the substrate treating apparatus.
摘要翻译：本文公开的基板处理装置实现了改善的生产量。根据本发明的基板处理装置包括并列布置的防反射膜形成块，抗蚀剂膜形成块和显影块。每个块包括化学处理模块，热处理模块和单个主要输送机构。主要运输机构在每个区块内运输基材。通过基板支架进行相邻块之间的基板的转移。每个块的主要运输机构不受邻接块主运输机构的运动的影响。因此，可以有效地输送基板，以提高基板处理装置的通过量。

2. 发明授权

US06873563B2 Semiconductor circuit device adaptable to plurality of types of packages 失效
标题翻译：适用于多种类型的封装的半导体电路器件
公开(公告)号：US06873563B2
公开(公告)日：2005-03-29
申请号：US10390886
申请日：2003-03-19
申请人： Makoto Suwa , Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto , Tetsuichiro Ichiguchi , Hideki Yonetani , Tsutomu Nagasawa , Zengcheng Tian
发明人： Makoto Suwa , Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto , Tetsuichiro Ichiguchi , Hideki Yonetani , Tsutomu Nagasawa , Zengcheng Tian
IPC分类号： H01L27/04 , G11C5/00 , G11C5/02 , G11C5/06 , G11C8/00 , G11C11/34 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/409 , H01L21/822 , H01L23/50 , H01L27/10 , H02J1/00
CPC分类号： G11C5/025 , G11C7/1045 , G11C8/10 , G11C11/406 , G11C11/40618 , G11C11/4093 , G11C2207/105 , G11C2211/4061 , H01L2224/32145 , H01L2924/01019 , H01L2924/01037 , H01L2924/01068 , H01L2924/01087 , H01L2924/13091 , H01L2924/00
摘要： Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.
摘要翻译：数据焊盘区域分别布置在矩形的半导体存储器芯片的四个分割区域中，并且根据字结构在四个划分的区域中的每一个中选择性地使用数据焊盘。因此，可以实现能够组装在单个芯片封装和多芯片封装中的半导体存储器芯片。

3. 发明授权

US06724679B2 Semiconductor memory device allowing high density structure or high performance 有权
标题翻译：半导体存储器件允许高密度结构或高性能
公开(公告)号：US06724679B2
公开(公告)日：2004-04-20
申请号：US10126622
申请日：2002-04-22
申请人： Tsutomu Nagasawa , Hideki Yonetani , Kozo Ishida , Shinichi Jinbo , Makoto Suwa , Tadaaki Yamauchi , Junko Matsumoto , Zengcheng Tian , Takeo Okamoto
发明人： Tsutomu Nagasawa , Hideki Yonetani , Kozo Ishida , Shinichi Jinbo , Makoto Suwa , Tadaaki Yamauchi , Junko Matsumoto , Zengcheng Tian , Takeo Okamoto
IPC分类号： G11C800
CPC分类号： G11C29/12005 , G11C8/12 , G11C29/26 , G11C2029/1206
摘要： A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.
摘要翻译：半导体存储器件包括存储体，预解码器，锁存电路，计数器，熔丝和缓冲器。存储体包括以行和列排列的多个存储单元。预解码器设置在半导体存储器件的中心部分。预解码器基于从缓冲器接收到的存储体地址产生用于选择每个存储体的预解码信号，并将预解码信号输出到存储体。预解码器产生用于基于存储体地址选择每个存储体的预解码信号，并将预解码信号输出到存储体。因此，可以减少中心部分的互连。

4. 发明授权

US06954103B2 Semiconductor device having internal voltage generated stably 失效
标题翻译：内部电压稳定的半导体装置
公开(公告)号：US06954103B2
公开(公告)日：2005-10-11
申请号：US10427968
申请日：2003-05-02
申请人： Tadaaki Yamauchi , Junko Matsumoto , Takeo Okamoto , Makoto Suwa , Tetsuichiro Ichiguchi , Hideki Yonetani , Tsutomu Nagasawa , Zengcheng Tian
发明人： Tadaaki Yamauchi , Junko Matsumoto , Takeo Okamoto , Makoto Suwa , Tetsuichiro Ichiguchi , Hideki Yonetani , Tsutomu Nagasawa , Zengcheng Tian
IPC分类号： H01L27/04 , G11C5/14 , G11C11/407 , G11C11/4074 , H01L21/822 , G05F1/46
CPC分类号： G11C11/4074 , G11C5/14
摘要： A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.
摘要翻译：根据电源电平设定信号切换产生高电压，中间电压和内部电源电压等内部电压的方式。当外部电源电压的电压低时，接收比较电路和辅助驱动晶体管的输出的电流驱动晶体管被强制设定在导通状态，外部电源电压在内部电源线。此时，比较电路的比较动作停止。当外部电源电压为高电平时，比较电路被激活，转换外部电源电压以产生内部电源线上的外围电源电压。

5. 发明授权

US06784718B2 Semiconductor device adaptable to a plurality of kinds of interfaces 有权
标题翻译：适用于多种界面的半导体装置
公开(公告)号：US06784718B2
公开(公告)日：2004-08-31
申请号：US10231132
申请日：2002-08-30
申请人： Takeo Okamoto , Tadaaki Yamauchi , Shinichi Jinbo , Makoto Suwa , Junko Matsumoto
发明人： Takeo Okamoto , Tadaaki Yamauchi , Shinichi Jinbo , Makoto Suwa , Junko Matsumoto
IPC分类号： H03L500
CPC分类号： G11C7/1087 , G11C5/147 , G11C7/1078 , G11C7/22 , G11C7/222
摘要： An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit. Even if the output power supply voltage varies to cause the input signal to change, whether the input signal is at H level or L level can accurately be determined and an internal signal is generated correctly
摘要翻译：输入电路包括：门电路，其接收决定输入信号的逻辑电平的输出电源电压或者接收输入信号的比较电路，以及取决于从不同于电源的焊盘提供的输出电源电压的基准电压用于输出电路的焊盘。即使输出电源电压变化，导致输入信号变化，输入信号是否处于H电平或L电平，可以准确地确定内部信号是否正确生成

6. 发明授权

US06765838B2 Refresh control circuitry for refreshing storage data 失效
标题翻译：刷新控制电路以刷新存储数据
公开(公告)号：US06765838B2
公开(公告)日：2004-07-20
申请号：US10209901
申请日：2002-08-02
申请人： Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto
发明人： Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto
IPC分类号： G11C700
CPC分类号： G11C11/40622 , G11C11/406
摘要： A refresh array activating signal is activated in accordance with a refresh request and specific address bit(s) of a refresh address. Specific lower bit(s) of a refresh address counter is (are) utilized as the specific address bit(s) of the refresh address, and the specific address bit(s) is (are) utilized as upper bit(s) of the refresh address. Thus, in the self-refresh mode, refresh can be performed for a prescribed address region at uniform intervals, with a lengthened refresh interval, consuming less current. A semiconductor memory device is provided which allows current consumption to be distributed on a time basis and to be reduce in a self-refresh mode is provided.
摘要翻译：根据刷新请求和刷新地址的特定地址位激活刷新阵列激活信号。刷新地址计数器的特定低位用作刷新地址的特定地址位，并且特定地址位用作（的）较高位刷新地址。因此，在自刷新模式下，可以以规定的地址区域以均匀的间隔进行刷新，延长刷新间隔，消耗较少的电流。提供了一种半导体存储器件，其提供了在时间基础上分布电流消耗并且提供了自刷新模式中的电流消耗。

7. 发明授权

US06714461B2 Semiconductor device with data output circuit having slew rate adjustable 有权
标题翻译：数据输出电路具有压摆率可调的半导体器件
公开(公告)号：US06714461B2
公开(公告)日：2004-03-30
申请号：US10139751
申请日：2002-05-07
申请人： Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto
发明人： Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto
IPC分类号： G11C700
CPC分类号： G11C7/1057 , G11C7/1045 , G11C7/1051 , G11C7/1066
摘要： Data for switching a slew rate of a data output circuit included in a data input/output circuit between a slew rate in a normal mode and a slow slew rate is stored in a mode register. According to the data stored in mode register, a slew rate setting signal is generated. According to a slew rate switching circuit, the slew rate of the data input/output circuit is switched between a slew rate in the normal mode and a slow slew rate slower than the slew rate in the normal mode. A data output circuit is achieved which occupies a small area, is capable of setting a slew rate slower than the slew rate in a normal mode and outputting data without causing an erroneous operation with a low consumption current even when the slew rate is adjusted.
摘要翻译：将数据输入/输出电路中包括的数据输出电路的转换速率转换为正常模式的转换速率和慢速转换速率之间的数据被存储在模式寄存器中。根据存储在模式寄存器中的数据，产生压摆率设定信号。根据转换速率切换电路，数据输入/输出电路的转换速率在正常模式下的转换速率和比正常模式下的转换速率慢的慢速转换速率之间切换。实现占用小面积的数据输出电路，即使在压摆率被调整的情况下，也能够将正常模式下的转换速度设定为比转换速度慢的输出速度，并输出数据而不引起低消耗电流的错误操作。

8. 发明授权

US06650582B2 Semiconductor memory device 失效
公开(公告)号：US06650582B2
公开(公告)日：2003-11-18
申请号：US10211339
申请日：2002-08-05
申请人： Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto
发明人： Junko Matsumoto , Tadaaki Yamauchi , Takeo Okamoto
IPC分类号： G11C700
CPC分类号： G11C29/34 , G11C7/1006 , G11C2029/1804 , G11C2029/2602
摘要： For a memory array, a main data bus commonly used for first and second data bit widths, and a main data bus used only for the second data bit width are disposed. According to a data bit width, connection between memory blocks and main data lines is switched. The main data buses are connected to write/read circuits, and expanding/compressing operation on data bits is performed by an expansion/compression circuit in a unit of a predetermined number of bits. Thus, with the same configuration irrespective of data bit width, compression of data bits in the multi-bit test can be performed to output the compression result to the same data terminal.

9. 发明授权

US5436848A Method of and device for transporting semiconductor substrate in semiconductor processing system 失效
标题翻译：在半导体处理系统中传输半导体衬底的方法和装置
公开(公告)号：US5436848A
公开(公告)日：1995-07-25
申请号：US47449
申请日：1993-04-15
申请人： Masami Nishida , Masahiro Himoto , Tetsuya Hamada , Noriaki Yokono , Takeo Okamoto
发明人： Masami Nishida , Masahiro Himoto , Tetsuya Hamada , Noriaki Yokono , Takeo Okamoto
IPC分类号： H01L21/00 , H01L21/677 , G06F19/00
CPC分类号： H01L21/67103 , H01L21/67745
摘要： A robot (12) takes a wafer (3f) out of an indexer (1) and then transports the same to a heat processing part (41). A wafer (3e), which has already introduced in the heat processing part (41) is took out thereof by the robot (5). The wafer (3f) is introduced in the heat processing part (41) after a waiting time (18a) so that an excess heat processing in the heat processing part (41) can be avoided. The wafer (3e) is transported to a processing part (43) and introduced therein by the robot (5). After the robot (5) repeats the similar processings in processing parts (13, 42, 44), it returns to the wafer transferring robot (12) to receive a next wafer. At that time, the robot (5) waits for a predetermined time thereby a cycle time is adjusted. After the waiting, the robot (5) takes out the wafer (3f), which has been introduced in the heat processing part (41), out thereof. Since the cycle time is set in common for different lots, the waiting times (18a, 18b) are set individually for each lot.
摘要翻译：机器人（12）将晶片（3f）从分度器（1）中取出，然后将其输送到热处理部分（41）。已经引入热处理部（41）的晶片（3e）被机器人（5）取出。在等待时间（18a）之后，将晶片（3f）引入热处理部（41），从而可以避免热处理部（41）中的过度热处理。将晶片（3e）输送到加工部（43）并由机器人（5）引入。在机器人（5）重复处理部件（13,42,44）中的类似处理之后，返回到晶片传送机器人（12）以接收下一晶片。此时，机器人（5）等待预定时间，从而调整循环时间。在等待之后，机器人（5）将已经引入热处理部分（41）中的晶片（3f）取出。由于循环时间对于不同的批次是共同设定的，因此为每个批次分别设置等待时间（18a，18b）。

10. 发明授权

US06813210B2 Semiconductor memory device requiring refresh operation 失效
标题翻译：需要刷新操作的半导体存储器件
公开(公告)号：US06813210B2
公开(公告)日：2004-11-02
申请号：US10300591
申请日：2002-11-21
申请人： Takeo Okamoto , Tetsuichiro Ichiguchi , Hideki Yonetani , Tsutomu Nagasawa , Tadaaki Yamauchi , Makoto Suwa , Junko Matsumoto , Zengcheng Tian
发明人： Takeo Okamoto , Tetsuichiro Ichiguchi , Hideki Yonetani , Tsutomu Nagasawa , Tadaaki Yamauchi , Makoto Suwa , Junko Matsumoto , Zengcheng Tian
IPC分类号： G11C700
CPC分类号： G11C7/04 , G11C11/406
摘要： The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.
摘要翻译：半导体存储器件包括用于确定自刷新操作的刷新周期的刷新定时器。刷新定时器包括电压调节器，环形振荡器和计数器。电压调节器产生具有正温度特性的偏置电压。环形振荡器根据偏置电压来改变脉冲信号的振荡周期。计数器对规定数量的脉冲信号进行计数，并产生用于执行刷新操作的刷新信号。因此，半导体存储器件根据温度变化而改变刷新周期，并且以适当的刷新周期执行刷新操作。

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