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1. 发明授权

US5323348A Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit 失效
标题翻译：具有多个存储器阵列并且包括用于修复故障位的冗余电路的半导体存储器件
公开(公告)号：US5323348A
公开(公告)日：1994-06-21
申请号：US767316
申请日：1991-09-30
申请人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
发明人： Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Mitsuya Kinoshita , Makoto Suwa , Shigeru Kikuda , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/409 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/848
摘要： Column repairing circuits 7a, 7b for repairing a DRAM in which there are defective memory cells in two columns are disclosed. The connection state of switching elements or circuits 51-5n, 61-6n, 71-7 (n+1), 81-8 (n+1) is determined as illustrated by appropriately disconnecting fuses in fuse links provided respectively in circuits 7a, 7b. Accordingly, column selecting lines Y2a and Y (n+1) b in memory array blocks 891a, 891b are not activated. The two repairing circuits 7a, 7b are provided spaced apart from each other on a semiconductor substrate, so that excessive concentration of fuse elements and switching elements or circuits is prevented.
摘要翻译：公开了用于修复其中存在两列不良存储器单元的DRAM的列修复电路7a，7b。开关元件或电路51-5n，61-6n，71-7（n + 1），81-8（n + 1）的连接状态通过适当地断开分别设置在电路7a， 7b。因此，存储器阵列块891a，891b中的列选择线Y2a和Y（n + 1）b未被激活。两个修复电路7a，7b在半导体衬底上彼此间隔开设置，从而防止了熔丝元件和开关元件或电路的过度集中。

2. 发明授权

US5321654A Semiconductor device having no through current flow in standby period 失效
标题翻译：半导体器件在待机期间没有通过电流流动
公开(公告)号：US5321654A
公开(公告)日：1994-06-14
申请号：US863975
申请日：1992-04-06
申请人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
发明人： Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Mori , Shigeru Kikuda , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： G11C11/408 , G11C5/14 , G11C7/22 , G11C8/18 , G11C11/401 , G11C11/409 , H01L21/822 , H01L27/04 , H01L27/10 , G11C7/00
CPC分类号： G11C7/22 , G11C5/14 , G11C8/18
摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.
摘要翻译：一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

3. 发明授权

US5357478A Semiconductor integrated circuit device including a plurality of cell array blocks 失效
标题翻译：包括多个单元阵列块的半导体集成电路装置
公开(公告)号：US5357478A
公开(公告)日：1994-10-18
申请号：US767332
申请日：1991-09-30
申请人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
发明人： Shigeru Kikuda , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Makoto Suwa , Mitsuya Kinoshita
IPC分类号： H01L21/822 , G11C5/02 , G11C11/401 , H01L27/04 , H01L27/10 , G11C8/00
CPC分类号： G11C5/025
摘要： A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
摘要翻译：在芯片上形成多个子芯片。输入/输出缓冲区布置在多个子芯片周围。每个子芯片包括子芯片控制电路区域和多个存储单元阵列块。每个存储单元阵列块包括存储单元阵列区域，行解码器和控制电路区域，读出放大器区域和输入/输出锁存区域。

4. 发明授权

US5574729A Redundancy circuit for repairing defective bits in semiconductor memory device 失效
标题翻译：用于修复半导体存储器件中的有缺陷的位的冗余电路
公开(公告)号：US5574729A
公开(公告)日：1996-11-12
申请号：US338817
申请日：1994-11-10
申请人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
发明人： Mitsuya Kinoshita , Shigeru Mori , Yoshikazu Morooka , Hiroshi Miyamoto , Shigeru Kikuda , Makoto Suwa
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , G06F11/00
CPC分类号： G11C29/848
摘要： A semiconductor memory device includes a plurality of memory blocks, i main row or column select lines extending over the plurality of memory blocks, and a decoder for selecting one of the main row or column select lines in accordance with an applied address signal. The decoder includes i outputs. Each of the memory blocks includes a plurality of memory cells arranged in rows and columns and at least (i+1) sub row or column select lines each for selecting one row or one column of memory cells. A shift redundancy circuit is provided for each of the memory blocks, for connecting the main row or column select line and the sub row or column select line. The shift redundancy circuit includes a switch circuit for connecting one main row or column select line to one of the plurality of adjacent sub row or column select lines, and a circuit for setting a connection path of the switch circuit. The shift redundancy circuit connects successively adjacent sub row or column select lines to main row or column select lines in one to one correspondence except a defective sub row or column select line associated with a defective bit.
摘要翻译：一种半导体存储器件包括多个存储块，i个在多个存储块上延伸的主行或列选择线，以及用于根据所施加的地址信号选择主行或列选择线中的一个的解码器。解码器包括i个输出。每个存储块包括排列成行和列的多个存储器单元和至少（i + 1）个子行或列选择线，每个用于选择一行或一列存储单元。为每个存储块提供移位冗余电路，用于连接主行或列选择线和子行或列选择线。移位冗余电路包括用于将一个主行或列选择线连接到多个相邻子行或列选择线中的一个的开关电路和用于设置开关电路的连接路径的电路。除了与有缺陷的位相关联的有缺陷的子行或列选择线之外，移位冗余电路将连续相邻的子行或列选择线以一对一的对应方式连接到主行或列选择线。

5. 发明授权

US5384784A Semiconductor memory device comprising a test circuit and a method of operation thereof 失效
标题翻译：半导体存储器件，包括测试电路及其操作方法
公开(公告)号：US5384784A
公开(公告)日：1995-01-24
申请号：US750040
申请日：1991-08-27
申请人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
发明人： Shigeru Mori , Makoto Suwa , Hiroshi Miyamoto , Yoshikazu Morooka , Shigeru Kikuda , Mitsuya Kinoshita
IPC分类号： G11C11/409 , G11C11/401 , G11C29/00 , G11C29/34 , G06F15/20
CPC分类号： G11C29/34
摘要： A semiconductor memory device includes a memory array. The bit line pairs of the odd number order in the memory array belong to a first group, and the bit line pairs of the even number order belong to a second group. A first amplifier is connected to each bit line pair. Corresponding to the first group, write buses read buses and a read/test circuit are provided. Corresponding to the second group, write buses read buses and a read/test circuit are provided. A column decoder selects a plurality of bit line pairs simultaneously at the time of testing. At the time of testing, each of the read/test circuits compares data read out from the plurality of bit line pairs belonging to the corresponding group with a given expected data for providing the comparison result.
摘要翻译：半导体存储器件包括存储器阵列。存储器阵列中奇数次序的位线对属于第一组，偶数顺序的位线对属于第二组。第一放大器连接到每个位线对。对应于第一组，写总线读总线和读/测电路。对应于第二组，写总线读总线和读/测电路。列解码器在测试时同时选择多个位线对。在测试时，每个读/测试电路将从属于相应组的多个位线对中读出的数据与给定的预期数据进行比较，以提供比较结果。

6. 发明授权

US5337272A Circuit for applying selected voltages to dynamic random access memory 失效
标题翻译：将选定电压应用于动态随机存取存储器有效老化和存储单元测试的电路
公开(公告)号：US5337272A
公开(公告)日：1994-08-09
申请号：US32554
申请日：1993-03-17
申请人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
发明人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , G11C11/40 , G11C11/407
CPC分类号： G11C29/50008 , G11C29/50 , G11C11/401
摘要： A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The selection circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.
摘要翻译：动态随机存取存储器（DRAM）包括用于选择用于老化的电压的选择电路。选择电路响应于外部控制信号而工作。当选择源电压（Vcc）时，经由电路73和传输栅极将电压（Vcc）提供给存储单元的一个电极，同时通过位线将地电位（Vss）提供给另一电极，一个晶体管。相反，当选择接地电位（Vss）时，在两个电极之间施加反向电压。以这种方式，可以在老化期间更可靠地检查插入在两个电极之间的绝缘体的绝缘性。

7. 发明授权

US5079743A Circuit for applying selected voltages to dynamic random access memory 失效
标题翻译：将动作选择电压应用于动态随机存取存储器的电路
公开(公告)号：US5079743A
公开(公告)日：1992-01-07
申请号：US436587
申请日：1989-11-15
申请人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
发明人： Makoto Suwa , Hiroshi Miyamoto , Shigeru Mori
IPC分类号： G11C11/404 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50
CPC分类号： G11C29/50008 , G11C29/50 , G11C11/401
摘要： A dynamic random access memory (DRAM) includes a selection circuit for selecting the voltages used for aging. The switching circuit operates responsive to external control signals. When a source voltage (Vcc) is selected, the voltage (Vcc) is supplied to one electrode of a memory cell via a circuit 73 and a transmission gate while a ground potential (Vss) is supplied to the other electrode via a bit line and a transistor. Conversely, when the ground potential (Vss) is selected, an inverted voltage is applied across the two electrodes. In this manner, the insulating properties of an insulator interposed between the two electrodes can be checked more reliably during aging.
摘要翻译：动态随机存取存储器（DRAM）包括用于选择用于老化的电压的选择电路。开关电路响应于外部控制信号而工作。当选择源电压（Vcc）时，经由电路73和传输栅极将电压（Vcc）提供给存储单元的一个电极，同时通过位线将地电位（Vss）提供给另一电极，一个晶体管。相反，当选择接地电位（Vss）时，在两个电极之间施加反向电压。以这种方式，可以在老化期间更可靠地检查插入在两个电极之间的绝缘体的绝缘性。

8. 发明授权

US4870620A Dynamic random access memory device with internal refresh 失效
标题翻译：具有内部刷新功能的动态随机存取存储器
公开(公告)号：US4870620A
公开(公告)日：1989-09-26
申请号：US141076
申请日：1988-01-05
申请人： Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada , Shigeru Mori , Tetsuya Aono
发明人： Tadato Yamagata , Hiroshi Miyamoto , Michihiro Yamada , Shigeru Mori , Tetsuya Aono
IPC分类号： G11C8/06 , G11C11/406
CPC分类号： G11C8/06 , G11C11/406
摘要： The switching circuit 4 receives external address signals EXT. A.sub.0 to A.sub.8 or output signals Q.sub.0 to Q.sub.8 from the refresh counter 2 and selects either of these signals in response to the clock signals .phi..sub.2 and .phi..sub.2 to apply the same to the address buffer 1. A plurality of N type field effect transistors, which operate in response to the clock signal .phi..sub.3, such as transistors 540, 54 and 548 are connected between each of the inputs of the switching circuit 4 for receiving the external address signals EXT. A.sub.0 to A.sub.8 and the ground V.sub.ss. Referring to the i-th circuit portion, before the switching circuit 4 applies a signal Q.sub.i from the refresh counter 2 to the address buffer 1, the transistor 54 turns on in response to the clock signal .phi..sub.3 and brings the input of the address buffer 1 to the voltage level of the ground V.sub.ss. When the switching circuit 4 is switched, the signal from the refresh counter 2 is correctly applied to the address buffer 1. Therefore, malfunctions of the address buffer 1 can be prevented.
摘要翻译：开关电路4接收外部地址信号EXT。 A0至A8或来自刷新计数器2的输出信号Q0至Q8，并响应于时钟信号phi 2和phi 2选择这些信号之一，以将其应用于地址缓冲器1.多个N型场效应晶体管，响应于时钟信号phi 3工作的时钟信号，例如晶体管540,54和548连接在开关电路4的每个输入端之间，用于接收外部地址信号EXT。 A0到A8和地面Vss。参考第i个电路部分，在开关电路4将来自刷新计数器2的信号Qi施加到地址缓冲器1之前，晶体管54响应于时钟信号phi3导通，并使地址缓冲器 1到地面Vss的电压电平。当切换电路4被切换时，来自刷新计数器2的信号被正确地施加到地址缓冲器1.因此，可以防止地址缓冲器1的故障。

9. 发明授权

US4780850A CMOS dynamic random access memory 失效
标题翻译： CMOS动态随机存取存储器
公开(公告)号：US4780850A
公开(公告)日：1988-10-25
申请号：US116285
申请日：1987-11-02
申请人： Hiroshi Miyamoto , Shigeru Mori , Michihiro Yamada , Tadato Yamagata
发明人： Hiroshi Miyamoto , Shigeru Mori , Michihiro Yamada , Tadato Yamagata
IPC分类号： G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4094
摘要： A dynamic random access memory comprises N channel sense amplifiers, P channel sense amplifiers and an equalizing MOSFET each provided for each of bit line pairs. The N channel sense amplifiers and the P channel sense amplifiers are operated by sense amplifier driving signals. In each of the N channel sense amplifiers, an MOSFET is connected between one of bit lines and an interconnection for transmitting a sense amplifier driving signal. In addition, a precharge potential generating circuit for generating a potential of (1/2)V.sub.CC is connected to the interconnection for transmitting the sense amplifier driving signal through a MOSFET. The bit line pairs are equalized by the equalizing MOSFET. Then, in each of the N channel sense amplifiers, the above described interconnection and one of the bit lines are connected to each other, and the above described interconnection and the precharge potential generating circuit are connected to each other. Therefore, the potentials on the bit line pairs and the above described interconnection are held at (1/2)V.sub.CC.
摘要翻译：动态随机存取存储器包括N个通道读出放大器，P沟道读出放大器和均匀化的MOSFET，每个均为每个位线对提供。 N沟道读出放大器和P沟道读出放大器由读出放大器驱动信号操作。在每个N沟道读出放大器中，MOSFET连接在位线之一和用于传输读出放大器驱动信号的互连之间。此外，用于产生（1/2）VCC的电位的预充电电位发生电路连接到用于通过MOSFET传输读出放大器驱动信号的互连。位线对由均衡MOSFET均衡。然后，在N个通道读出放大器的每一个中，上述互连和一个位线彼此连接，并且上述互连和预充电电势产生电路彼此连接。因此，位线对上的电位和上述互连保持在（1/2）VCC。

10. 发明授权

US4984054A Electric fuse for a redundancy circuit 失效
标题翻译：电熔丝用于冗余电路
公开(公告)号：US4984054A
公开(公告)日：1991-01-08
申请号：US481683
申请日：1990-02-20
申请人： Michihiro Yamada , Hiroshi Miyamoto , Tadato Yamagata , Shigeru Mori
发明人： Michihiro Yamada , Hiroshi Miyamoto , Tadato Yamagata , Shigeru Mori
IPC分类号： H01L21/82 , H01H37/76 , H01L21/3205 , H01L23/525 , H01L27/10
CPC分类号： H01L23/5256 , H01L2924/0002
摘要： The present invention comprises a field oxide film formed on a silicon substrate, an underlying film of polycrystal silicon formed on a portion thereof and an insulating film formed so as to cover the field oxide film comprising the underlying film. A surface stepped portion of the insulating film is formed by a portion with an underlying film and a portion without an underlying film under the insulating film, and a blowout portion of a fuse is formed along the surface stepped portion. There are terminal portions at both ends of the blowout portion of the fuse and an aluminum line is connected thereto. In addition, the whole portions comprising the fuse portion are covered with another insulating film and the whole is protected. The fuse is employed as one example in a redundancy circuit of a MOS dynamic RAM having redundancy memory cells.
摘要翻译：本发明包括形成在硅衬底上的场氧化物膜，形成在其一部分上的多晶硅的下面的膜和形成为覆盖包括下面的膜的场氧化物膜的绝缘膜。绝缘膜的表面阶梯部分由具有下面的膜的部分和在绝缘膜下方没有下面的膜的部分形成，并且沿表面台阶形成熔丝的吹出部分。在保险丝的吹出部分的两端有端子部分，铝线连接到其上。此外，包括熔丝部分的整个部分被另一绝缘膜覆盖，并且整体被保护。在具有冗余存储单元的MOS动态RAM的冗余电路中采用熔丝作为一个例子。

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