专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07736983B2 High threshold NMOS source-drain formation with As, P and C to reduce damage 有权
标题翻译：具有As，P和C的高阈值NMOS源极 - 漏极形成，以减少损伤
公开(公告)号：US07736983B2
公开(公告)日：2010-06-15
申请号：US11972417
申请日：2008-01-10
申请人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
发明人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
IPC分类号： H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26586 , H01L21/823418 , H01L29/0847 , H01L29/6659 , H01L29/7833
摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implantation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed.
摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。碳注入通常用于减少NLDD中的磷扩散，但有助于栅极二极管泄漏（GDL）。在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。还公开了在NSD中具有小于1×1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管。

2. 发明申请

US20090004803A1 MULTI-STAGE IMPLANT TO IMPROVE DEVICE CHARACTERISTICS 有权
标题翻译：多阶段植入物提高装置特性
公开(公告)号：US20090004803A1
公开(公告)日：2009-01-01
申请号：US11769058
申请日：2007-06-27
申请人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
发明人： Manoj Mehrotra , Stan Ashburn , Shaoping Tang
IPC分类号： G11C11/34 , H01L21/8238
CPC分类号： G11C11/412 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/7833
摘要： One aspect of the inventors' concept relates to a method of forming a semiconductor device. In this method, a gate structure is formed over a semiconductor body. A source/drain mask is patterned over the semiconductor body implanted source and drain regions are formed that are associated with the gate structure. After forming the implanted source and drain regions, a multi-stage implant is performed on the source and drain regions that comprises at least two implants where the dose and energy of the first implant varies from the dose and energy of the second implant. Other methods and devices are also disclosed.
摘要翻译：本发明人的概念的一个方面涉及形成半导体器件的方法。在该方法中，在半导体本体上形成栅极结构。源极/漏极掩模在半导体本体注入源上形成图案，并且形成与栅极结构相关联的漏极区。在形成植入的源区和漏区之后，在包括至少两个植入物的源极和漏极区域上执行多级注入，其中第一注入的剂量和能量与第二植入物的剂量和能量不同。还公开了其它方法和装置。

3. 发明申请

US20060024910A1 Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI) 有权
标题翻译：在CMOS技术中使用浅沟槽隔离（STI）来设计反向窄宽度效应（INWE）的方法，
公开(公告)号：US20060024910A1
公开(公告)日：2006-02-02
申请号：US10899664
申请日：2004-07-27
申请人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
发明人： Amitava Chatterjee , Alwin Tsao , Manuel Quevedo-Lopez , Jong Yoon , Shaoping Tang
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/823878
摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).
摘要翻译：公开了一种形成隔离结构的方法（200），并且包括在与隔离区域相关联的半导体本体（214）中形成隔离沟槽，并用植入物掩模材料（216）填充隔离沟槽的底部。在其底部填充有注入掩模材料之后，在隔离沟槽（218）中进行成角度的离子注入，从而在半导体本体中形成阈值电压补偿区域。随后，隔离沟槽填充有电介质材料（220）。

4. 发明申请

US20130105904A1 RADIATION HARDENED INTEGRATED CIRCUIT 有权
标题翻译：辐射硬化集成电路
公开(公告)号：US20130105904A1
公开(公告)日：2013-05-02
申请号：US13286293
申请日：2011-11-01
申请人： RICHARD G. ROYBAL , SHARIQ ARSHAD , SHAOPING TANG , JAMES FRED SALZMAN
发明人： RICHARD G. ROYBAL , SHARIQ ARSHAD , SHAOPING TANG , JAMES FRED SALZMAN
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823892 , H01L27/0921 , H01L27/0928
摘要： A method of forming an integrated circuit (IC) includes providing a substrate having a topside semiconductor surface, wherein the topside semiconductor surface includes at least one of N+ buried layer regions and P+ buried layer regions. An epitaxial layer is grown on the topside semiconductor surface. Pwells are formed in the epitaxial layer. Nwells are formed in the epitaxial layer. NMOS devices are formed in and over the pwells, and PMOS devices are formed in and over the nwells.
摘要翻译：形成集成电路（IC）的方法包括提供具有顶侧半导体表面的衬底，其中顶侧半导体表面包括N +掩埋层区域和P +掩埋层区域中的至少一个。在顶侧半导体表面上生长外延层。孔在外延层中形成。 N外延层形成。 NMOS器件形成在阱的内部和上方，并且PMOS器件形成在n阱中和上方。

5. 发明授权

US06933203B2 Methods for improving well to well isolation 有权
标题翻译：改善井良好隔离的方法
公开(公告)号：US06933203B2
公开(公告)日：2005-08-23
申请号：US10299525
申请日：2002-11-19
申请人： Zhiqiang Wu , Shaoping Tang , Jau-Yuann Yang
发明人： Zhiqiang Wu , Shaoping Tang , Jau-Yuann Yang
IPC分类号： H01L21/761 , H01L21/762 , H01L21/8234 , H01L21/00
CPC分类号： H01L21/76237 , H01L21/761 , H01L21/823481
摘要： Methods are provided for forming wells in a semiconductor wafer, in which p-wells and n-wells are formed in a substrate, and first p-type dopants are implanted into n-well regions while an n-well mask remains over the wafer to selectively decrease a substrate resistivity in the n-well regions beneath the n-wells. A subsequent blanket implantation provides second p-type dopants into isolation regions of the substrate beneath isolation structures, where the first and second p-type dopants improve well to well isolation without addition of extra masks to the fabrication process.
摘要翻译：提供了用于在半导体晶片中形成阱的方法，其中在衬底中形成p阱和n阱，并且将第一p型掺杂剂注入到n阱区域中，同时n阱掩模保留在晶片上，选择性地降低n阱下面的n阱区中的衬底电阻率。随后的覆盖植入在隔离结构下方的衬底的隔离区域中提供第二p型掺杂剂，其中第一和第二p型掺杂剂改善了良好的良好隔离，而没有向制造工艺添加额外的掩模。

6. 发明授权

US06930007B2 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
标题翻译：用于改善晶体管性能的前S / D退火选择性氮化物/氧化物复合帽的集成
公开(公告)号：US06930007B2
公开(公告)日：2005-08-16
申请号：US10662850
申请日：2003-09-15
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/00 , H01L21/3205 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/8238 , H01L21/84 , H01L29/08 , H01L29/76 , H01L29/78
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
摘要翻译：本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

7. 发明申请

US20050118770A1 Method for introducing hydrogen into a channel region of a metal oxide semiconductor (MOS) device 审中-公开
标题翻译：将氢引入金属氧化物半导体（MOS）器件的沟道区域的方法
公开(公告)号：US20050118770A1
公开(公告)日：2005-06-02
申请号：US10956864
申请日：2004-10-01
申请人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
发明人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
IPC分类号： H01L21/30 , H01L21/324 , H01L21/336 , H01L29/78 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/3003 , H01L21/324 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (230) over a substrate (210) and forming at least a portion of source/drain regions in the substrate (210). The method further includes annealing the substrate containing the at least a portion of source/drain regions in the presence of hydrogen, and forming an interlevel dielectric layer over the substrate (210) having previously been annealed in the presence of hydrogen.
摘要翻译：本发明提供一种半导体器件的制造方法及其制造方法。除了其他步骤之外，制造半导体器件的方法包括在衬底（210）上形成栅极结构（230）并且形成衬底（210）中的源极/漏极区域的至少一部分。该方法还包括在存在氢的情况下对包含至少一部分源极/漏极区的衬底进行退火，以及在预先在氢气存在下预先退火的衬底（210）上形成层间电介质层。

8. 发明授权

US06855984B1 Process to reduce gate edge drain leakage in semiconductor devices 有权
标题翻译：降低半导体器件漏极漏极的工艺
公开(公告)号：US06855984B1
公开(公告)日：2005-02-15
申请号：US10697510
申请日：2003-10-30
申请人： Zhiqiang Wu , Shaoping Tang , Song Zhao
发明人： Zhiqiang Wu , Shaoping Tang , Song Zhao
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L29/78 , H01L29/76
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823842 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/6656 , H01L29/7833
摘要： The present invention employs a no mask, blanket implant of an n-type implant after formation of active regions in NMOS devices. As a result, the implanted n-type dopants counteract portions of strongly p-type HALO or pocket regions creating a smoother dopant profile or transition from a portion of the active regions to the channel. However, the blanket implant is performed at a relatively low energy so as to not significantly alter one or more other portions of the active regions to other portions of the device.
摘要翻译：本发明在NMOS器件中形成有源区之后采用n型注入的无掩模，覆盖式注入。结果，注入的n型掺杂剂抵消了强p型HALO或凹坑区域的部分，从而产生了更平滑的掺杂物分布或从有源区域的一部分到沟道的转变。然而，橡皮布注入在相对较低的能量下进行，以便不会将活性区的一个或多个其它部分显着地改变到该装置的其它部分。

9. 发明申请

US20090179280A1 HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE 有权
标题翻译：具有As，P和C的高阈值NMOS源 - 漏极形成以减少损害
公开(公告)号：US20090179280A1
公开(公告)日：2009-07-16
申请号：US11972417
申请日：2008-01-10
申请人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
发明人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26586 , H01L21/823418 , H01L29/0847 , H01L29/6659 , H01L29/7833
摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed
摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。碳植入通常用于减少NLDD中的磷扩散，但有助于门极二极管泄漏（GDL）。在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。还公开了在NSD中具有小于1.1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管

10. 发明申请

US20070176263A1 Nwell to nwell isolation 有权
标题翻译：保持隔离
公开(公告)号：US20070176263A1
公开(公告)日：2007-08-02
申请号：US11343695
申请日：2006-01-31
申请人： Shaoping Tang , Zhiqiang Wu
发明人： Shaoping Tang , Zhiqiang Wu
IPC分类号： H01L29/00 , H01L21/425
CPC分类号： H01L21/26513 , H01L21/2658 , H01L21/266 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892
摘要： Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions subsequently formed in the substrate. The blanket implantations are performed through isolation regions in the substrate so that the p type dopants are implanted to depths sufficient to separate the nwell regions. This increased concentration of p type dopants helps to mitigate leakage between the nwell regions as the nwell regions are brought closer together to increase packing densities.
摘要翻译：执行一个或多个p型掺杂剂到半导体衬底中的多次覆盖注入，以便于随后在衬底中形成的n阱区之间的隔离。通过衬底中的隔离区域进行覆盖注入，使得p型掺杂剂被植入足以分离nwell区域的深度。这种增加的p型掺杂剂的浓度有助于减轻nwell区域之间的泄漏，因为nwell区域靠近在一起以增加包装密度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式