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1. 发明授权

US06767810B2 Method to increase substrate potential in MOS transistors used in ESD protection circuits 有权
标题翻译：在ESD保护电路中使用的MOS晶体管中增加衬底电位的方法
公开(公告)号：US06767810B2
公开(公告)日：2004-07-27
申请号：US10629514
申请日：2003-07-29
申请人： Craig T. Salling , Amitava Chatterjee , Youngmin Kim
发明人： Craig T. Salling , Amitava Chatterjee , Youngmin Kim
IPC分类号： H01L218249
CPC分类号： H01L27/0277
摘要： An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad. In the first embodiment, the space includes a dummy gate; in the second embodiment, an isolation region; in the third embodiment, the space a protected, stable surface.
摘要翻译：位于半导体芯片表面的隔离沟槽之间的集成电路，包括具有第一电阻率的第一导电类型的第一阱。该第一阱具有比第一电阻率更高的电阻率的浅埋入区，在隔离沟槽之间延伸并由补偿掺杂工艺产生。电路还包括延伸到隔离沟槽之间的表面的相反导电类型的第二阱，具有接触区域并与第一阱的浅埋入区域基本上平行于表面形成结。最后，电路具有位于第二阱中的MOS晶体管，与接触区域间隔开，并且在表面具有源极，栅极和漏极区域。该空间是预定的，以在I / O晶体管中产生一个小的电压降，用于调节信号和对焊盘的功率，或者ESD电路中的大的电压降，用于保护连接到焊盘的有源电路。在第一实施例中，空间包括虚拟门; 在第二实施例中，隔离区域; 在第三实施例中，空间是受保护的，稳定的表面。

2. 发明授权

US06937501B2 Writing to ferroelectric memory devices 有权
公开(公告)号：US06937501B2
公开(公告)日：2005-08-30
申请号：US10679616
申请日：2003-10-06
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C11/22 , H01L27/115 , H01L27/12
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/1203
摘要： A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line, and other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.

3. 发明授权

US06900969B2 ESD protection with uniform substrate bias 有权
标题翻译：具有均匀衬底偏置的ESD保护
公开(公告)号：US06900969B2
公开(公告)日：2005-05-31
申请号：US10316494
申请日：2002-12-11
申请人： Craig T. Salling , Roger A. Cline
发明人： Craig T. Salling , Roger A. Cline
IPC分类号： H01L27/02 , H02H3/20 , H02H9/00
CPC分类号： H01L27/0277
摘要： Protection circuitry (100) for protecting an integrated circuit against an ESD pulse is provided. The protection circuitry (100) includes a discharge circuitry (101) on a substrate (106) that discharges an ESD pulse to the integrated circuit to ground (104a). The protection circuitry (100) also includes a drive circuitry (102) that uses a portion of the ESD pulse voltage to bias the substrate (106) using a first guard ring (110) in the substrate (106), which surrounds the discharge circuitry (101) and drive circuitry (102). The protection circuitry (100) further includes a second guard ring (120) in substrate (106), which surrounds the first guard ring (110) and connects to Vss/ground potential (104c), thereby providing uniformity of the substrate bias.
摘要翻译：提供了用于保护集成电路免受ESD脉冲的保护电路（100）。保护电路（100）包括在衬底（106）上的放电电路（101），其将集成电路的ESD脉冲放电到地（104a）。保护电路（100）还包括使用ESD脉冲电压的一部分来使用衬底（106）中的第一保护环（110）来偏置衬底（106）的驱动电路（102），其围绕放电电路（101）和驱动电路（102）。保护电路（100）还包括衬底（106）中的第二保护环（120），其围绕第一保护环（110）并且连接到Vss /接地电位（104c），从而提供衬底偏置的均匀性。

4. 发明授权

US06882560B2 Reading ferroelectric memory cells 有权
标题翻译：读铁电记忆体
公开(公告)号：US06882560B2
公开(公告)日：2005-04-19
申请号：US10679544
申请日：2003-10-06
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C11/22 , H01L27/115 , H01L27/12
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/1203
摘要： A first fraction of a programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to other word lines coupled to control gates of non-selected memory cells. The first fraction of the programming voltage is applied to a first program line coupled to a first source/drain region of the selected memory cell and to other program lines coupled to first source/drain regions of non-selected memory cells. A second fraction of the programming voltage is applied to a first bit line coupled to a second source/drain region of the selected memory cell and to other bit lines coupled to second source/drain regions of non-selected memory cells.
摘要翻译：编程电压的第一分数被施加到耦合到铁电存储器单元阵列中的所选铁电存储器单元的控制栅极的第一字线。等于编程电压的栅极/源极电压足以反转每个存储单元的极性。接地电位被施加到耦合到未选择的存储器单元的控制栅极的其它字线。编程电压的第一部分被施加到耦合到所选择的存储器单元的第一源极/漏极区域的第一编程线以及耦合到未选择存储器单元的第一源极/漏极区域的其它编程线。编程电压的第二部分被施加到耦合到所选择的存储器单元的第二源极/漏极区域的第一位线和耦合到未选择的存储器单元的第二源极/漏极区域的其它位线。

5. 发明授权

US06791862B2 Junction-isolated depletion mode ferroelectric memory devices 失效
标题翻译：结型隔离耗尽型铁电存储器件
公开(公告)号：US06791862B2
公开(公告)日：2004-09-14
申请号：US10339503
申请日：2003-01-09
申请人： Craig T. Salling , Brian W. Huber
发明人： Craig T. Salling , Brian W. Huber
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11585 , H01L27/1159 , H01L29/78391
摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
摘要翻译：耗尽型铁电晶体管适合用作非易失性存储单元。描述了具有夹在晶体管的位线和源极/漏极区之间的二极管的各种实施例，用于增加读取干扰的余量。描述具有阵列架构的各种附加实施例，使得共享相同位线的两个存储器单元也共享相同的程序行。使用这种配置，非选择的单元容易地被提供有足够的栅极/源极电压，以便在对所选择的单元的读取和写入操作期间将单元维持在去激活状态。

6. 发明授权

US06665206B2 Array architecture for depletion mode ferroelectric memory devices 有权
公开(公告)号：US06665206B2
公开(公告)日：2003-12-16
申请号：US10205989
申请日：2002-07-26
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/1203
摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments have an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

7. 发明授权

US06587365B1 Array architecture for depletion mode ferroelectric memory devices 有权
公开(公告)号：US06587365B1
公开(公告)日：2003-07-01
申请号：US09653074
申请日：2000-08-31
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/1203
摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments have an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

8. 发明授权

US07236387B2 Writing to ferroelectric memory devices 有权
标题翻译：写入铁电存储器件
公开(公告)号：US07236387B2
公开(公告)日：2007-06-26
申请号：US11130598
申请日：2005-05-17
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C11/22
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/1203
摘要： A ground potential is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A fraction of a programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line. The programming voltage is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line and to other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
摘要翻译：接地电位施加到耦合到铁电存储器单元阵列中的所选铁电存储器单元的控制栅极的第一字线。编程电压的一小部分被施加到耦合到与第一字线不相关联的未选择的存储器单元的控制栅极的其它字线。编程电压被施加到耦合到所选择的存储器单元的第一源极/漏极区域的第一编程线和耦合到所选择的存储器单元的第二源极/漏极区域的第一位线。编程电压的一小部分被施加到耦合到与第一编程线不相关联的未选择的存储器单元的第一源极/漏极区域和耦合到未选择的存储器单元的第二源极/漏极区域的其它位线的其它程序线路不与第一位线相关联。

9. 发明授权

US07123503B2 Writing to ferroelectric memory devices 有权
标题翻译：写入铁电存储器件
公开(公告)号：US07123503B2
公开(公告)日：2006-10-17
申请号：US11130663
申请日：2005-05-17
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C11/22
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/1203
摘要： A programming voltage is applied to a first word line coupled to a control gate of a selected ferroelectric memory cell in an array of ferroelectric memory cells. A gate/source voltage equal to the programming voltage is sufficient to reverse polarity of each memory cell. A ground potential is applied to a first program line coupled to a first source/drain region of the selected memory cell and to a first bit line coupled to a second source/drain region of the selected memory cell. A fraction of the programming voltage is applied to other word lines coupled to control gates of non-selected memory cells not associated with the first word line, other program lines coupled to first source/drain regions of non-selected memory cells not associated with the first program line, and other bit lines coupled to second source/drain regions of non-selected memory cells not associated with the first bit line.
摘要翻译：将编程电压施加到耦合到铁电存储器单元阵列中的所选铁电存储器单元的控制栅极的第一字线。等于编程电压的栅极/源极电压足以反转每个存储单元的极性。接地电位被施加到耦合到所选择的存储器单元的第一源极/漏极区域的第一编程线和耦合到所选择的存储器单元的第二源极/漏极区域的第一位线。编程电压的一小部分被施加到耦合到与第一字线不相关联的未选择的存储器单元的控制栅极的其它字线，耦合到与第一字线不相关联的未选择的存储器单元的第一源极/漏极区域的其它编程线第一编程线和耦合到与第一位线不相关联的未选择的存储器单元的第二源极/漏极区域的其它位线。

10. 发明授权

US06944043B2 Junction-isolated depletion mode ferroelectric memory devices 有权
标题翻译：结型隔离耗尽型铁电存储器件
公开(公告)号：US06944043B2
公开(公告)日：2005-09-13
申请号：US10339041
申请日：2003-01-09
申请人： Craig T. Salling , Brian W. Huber
发明人： Craig T. Salling , Brian W. Huber
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11585 , H01L27/1159 , H01L29/78391
摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
摘要翻译：耗尽型铁电晶体管适合用作非易失性存储单元。描述了具有夹在晶体管的位线和源极/漏极区之间的二极管的各种实施例，用于增加读取干扰的余量。描述具有阵列架构的各种附加实施例，使得共享相同位线的两个存储器单元也共享相同的程序行。使用这种配置，非选择的单元容易地被提供有足够的栅极/源极电压，以便在对所选择的单元的读取和写入操作期间将单元维持在去激活状态。

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