专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07826291B2 Precharge and evaluation phase circuits for sense amplifiers 有权
标题翻译：读出放大器的预充电和评估相位电路
公开(公告)号：US07826291B2
公开(公告)日：2010-11-02
申请号：US12174307
申请日：2008-07-16
申请人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
发明人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C16/28
摘要： A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.
摘要翻译：用于存储读出放大器的预充电和评估电路包括具有耦合到电源电位的源极的第一预充电相晶体管，耦合到预充电控制线的栅极和漏极。第二预充电相晶体管具有耦合到第一预充电相晶体管的漏极的漏极，源极和通过反馈电路耦合到源极的栅极。第一读取相晶体管具有耦合到电源电位的源极，以及耦合到比较器的栅极和漏极。第二读取相位晶体管具有耦合到第一读取相位晶体管的漏极的漏极，耦合到第二预充电相位晶体管的源极的栅极，以及耦合到第二读取相位晶体管的源极的栅极，一个反馈电路。列解码器耦合到第二预充电相位和第二读相晶体管的源极。

2. 发明申请

US20100014370A1 PRECHARGE AND EVALUATION PHASE CIRCUITS FOR SENSE AMPLIFIERS 有权
标题翻译：用于感知放大器的预处理和评估相位电路
公开(公告)号：US20100014370A1
公开(公告)日：2010-01-21
申请号：US12174307
申请日：2008-07-16
申请人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
发明人： Lorenzo Bedarida , Fabio Tassan Caser , Mauro Chinosi , Donato Ferrario
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08 , G11C16/28
摘要： A precharge and evaluation circuit for a memory sense amplifier includes a first precharge-phase transistor having a source coupled to a power-supply potential, a gate coupled to a precharge control line, and a drain. A second precharge-phase transistor has a drain coupled to the drain of the first precharge-phase transistor, a source, and a gate coupled to the source through a feedback circuit. A first read-phase transistor has a source coupled to the power-supply potential, and a gate and drain coupled to a comparator. A second read-phase transistor has a drain coupled to the drain of the first read-phase transistor, a source coupled to the source of the second precharge-phase transistor, and a gate coupled to the source of the second read-phase transistor through a feedback circuit. A column decoder is coupled to the sources of the second precharge-phase and second read-phase transistors.
摘要翻译：用于存储读出放大器的预充电和评估电路包括具有耦合到电源电位的源极的第一预充电相晶体管，耦合到预充电控制线的栅极和漏极。第二预充电相晶体管具有耦合到第一预充电相晶体管的漏极的漏极，源极和通过反馈电路耦合到源极的栅极。第一读取相晶体管具有耦合到电源电位的源极，以及耦合到比较器的栅极和漏极。第二读取相位晶体管具有耦合到第一读取相位晶体管的漏极的漏极，耦合到第二预充电相位晶体管的源极的栅极，以及耦合到第二读取相位晶体管的源极的栅极，一个反馈电路。列解码器耦合到第二预充电相位和第二读相晶体管的源极。

3. 发明申请

US20080101133A1 ADAPTIVE GATE VOLTAGE REGULATION 有权
标题翻译：自适应门电压调节
公开(公告)号：US20080101133A1
公开(公告)日：2008-05-01
申请号：US11554797
申请日：2006-10-31
申请人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
发明人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C5/14
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
摘要翻译：存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

4. 发明授权

US07430150B2 Method and system for providing sensing circuitry in a multi-bank memory device 有权
标题翻译：用于在多存储体存储器件中提供感测电路的方法和系统
公开(公告)号：US07430150B2
公开(公告)日：2008-09-30
申请号：US11123544
申请日：2005-05-05
申请人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
发明人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C11/34 , G11C16/06 , G11C7/00 , G11C7/02 , G11C7/06
CPC分类号： G11C8/12 , G11C5/025 , G11C7/06 , G11C16/26
摘要： A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.
摘要翻译：描述了一种用于提供多存储体存储器的方法和系统。该方法和系统包括提供多个银行。多个存储体中的每一个包括包括多个存储单元和模拟感测电路的至少一个阵列。该方法和系统还包括提供与多个存储体耦合的公共数字感测电路。

5. 发明申请

US20060083097A1 Method and system for providing sensing circuitry in a multi-bank memory device 有权
标题翻译：用于在多存储体存储器件中提供感测电路的方法和系统
公开(公告)号：US20060083097A1
公开(公告)日：2006-04-20
申请号：US11123544
申请日：2005-05-05
申请人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
发明人： Massimiliano Frulio , Stefano Sivero , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C5/025 , G11C7/06 , G11C16/26
摘要： A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The method and system further include providing common digital sensing circuitry coupled with the plurality of banks.
摘要翻译：描述了一种用于提供多存储体存储器的方法和系统。该方法和系统包括提供多个银行。多个存储体中的每一个包括包括多个存储单元和模拟感测电路的至少一个阵列。该方法和系统还包括提供与多个存储体耦合的公共数字感测电路。

6. 发明授权

US07417904B2 Adaptive gate voltage regulation 有权
标题翻译：自适应栅极电压调节
公开(公告)号：US07417904B2
公开(公告)日：2008-08-26
申请号：US11554797
申请日：2006-10-31
申请人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
发明人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C5/14
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
摘要翻译：存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

7. 发明授权

US06809575B2 Temperature-compensated current reference circuit 有权
标题翻译：温度补偿电流参考电路
公开(公告)号：US06809575B2
公开(公告)日：2004-10-26
申请号：US10407622
申请日：2003-04-03
申请人： Giorgio Oddone , Lorenzo Bedarida , Mauro Chinosi
发明人： Giorgio Oddone , Lorenzo Bedarida , Mauro Chinosi
IPC分类号： G05F110
CPC分类号： G05F3/245
摘要： A circuit comprises an amplifier having first output node comprising a first n-channel MOS transistor and a second output node comprising a second n-channel MOS transistor. A first p-channel MOS transistor is coupled to a supply potential, and the second output node. A first PNP bipolar transistor is coupled to the first p-channel MOS transistor through a first resistor and to the second n-channel MOS transistor and to ground. A second PNP bipolar transistor is coupled to the first p-channel MOS transistor through a second resistor in series with a third resistor and to ground. The first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor is coupled to the first p-channel MOS transistor, to ground through a fourth resistor, and to either a reference potential or to the common node between the second and third resistors.
摘要翻译：一种电路包括具有包括第一n沟道MOS晶体管的第一输出节点和包括第二n沟道MOS晶体管的第二输出节点的放大器。第一p沟道MOS晶体管耦合到电源电位和第二输出节点。第一PNP双极晶体管通过第一电阻器和第二n沟道MOS晶体管耦合到第一p沟道MOS晶体管并接地。第二PNP双极晶体管通过与第三电阻器串联的第二电阻器并接地耦合到第一p沟道MOS晶体管。第一n沟道MOS晶体管耦合到第二和第三电阻之间的公共节点。第三n沟道MOS晶体管被耦合到第一p沟道MOS晶体管，通过第四电阻器接地，并且连接到参考电位或第二和第三电阻器之间的公共节点。

8. 发明授权

US07782695B2 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US07782695B2
公开(公告)日：2010-08-24
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

9. 发明申请

US20080170455A1 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US20080170455A1
公开(公告)日：2008-07-17
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

10. 发明授权

US08120963B2 Method and system for program pulse generation during programming of nonvolatile electronic devices 有权
标题翻译：在非易失性电子设备编程过程中编程脉冲产生的方法和系统
公开(公告)号：US08120963B2
公开(公告)日：2012-02-21
申请号：US12535455
申请日：2009-08-04
申请人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
发明人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译：在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式