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1. 发明申请

US20080101133A1 ADAPTIVE GATE VOLTAGE REGULATION 有权
标题翻译：自适应门电压调节
公开(公告)号：US20080101133A1
公开(公告)日：2008-05-01
申请号：US11554797
申请日：2006-10-31
申请人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
发明人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C5/14
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
摘要翻译：存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

2. 发明授权

US07417904B2 Adaptive gate voltage regulation 有权
标题翻译：自适应栅极电压调节
公开(公告)号：US07417904B2
公开(公告)日：2008-08-26
申请号：US11554797
申请日：2006-10-31
申请人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
发明人： Stefano Sivero , Stefano Surico , Fabio Tassan Caser , Mauro Chinosi
IPC分类号： G11C5/14
CPC分类号： G11C16/10 , G11C16/0483
摘要： A memory device generates a select voltage and an unselect voltage on bit lines and generates a bit line select voltage having a magnitude less than the unselect voltage so that the application of the bit line select voltage to a gate of a transistor receiving the select voltage causes the transistor to conduct, and the application of the bit line select voltage to a gate of a transistor receiving the unselect voltage biases the transistor off.
摘要翻译：存储器件在位线上产生选择电压和取消选择电压，并产生具有小于未选择电压的幅度的位线选择电压，从而将位线选择电压施加到接收选择电压的晶体管的栅极导致晶体管导通，并且将位线选择电压施加到接收去选择电压的晶体管的栅极偏置晶体管。

3. 发明申请

US20060077714A1 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US20060077714A1
公开(公告)日：2006-04-13
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

4. 发明申请

US20080165585A1 ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES 有权
标题翻译：用于NAND型闪存存储器的擦除验证方法
公开(公告)号：US20080165585A1
公开(公告)日：2008-07-10
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

5. 发明授权

US07345921B2 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US07345921B2
公开(公告)日：2008-03-18
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

6. 发明申请

US20120106250A1 METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES 有权
标题翻译：非线性电子设备编程过程中的程序脉冲发生方法与系统
公开(公告)号：US20120106250A1
公开(公告)日：2012-05-03
申请号：US13346979
申请日：2012-01-10
申请人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
发明人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译：在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。

7. 发明授权

US08120963B2 Method and system for program pulse generation during programming of nonvolatile electronic devices 有权
标题翻译：在非易失性电子设备编程过程中编程脉冲产生的方法和系统
公开(公告)号：US08120963B2
公开(公告)日：2012-02-21
申请号：US12535455
申请日：2009-08-04
申请人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
发明人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译：在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。

8. 发明申请

US20090290424A1 METHOD AND SYSTEM FOR PROGRAM PULSE GENERATION DURING PROGRAMMING OF NONVOLATILE ELECTRONIC DEVICES 有权
标题翻译：非线性电子设备编程过程中的程序脉冲发生方法与系统
公开(公告)号：US20090290424A1
公开(公告)日：2009-11-26
申请号：US12535455
申请日：2009-08-04
申请人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
发明人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
IPC分类号： G11C16/04 , G06F1/04
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译：在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。

9. 发明授权

US07570519B2 Method and system for program pulse generation during programming of nonvolatile electronic devices 有权
标题翻译：在非易失性电子设备编程过程中编程脉冲产生的方法和系统
公开(公告)号：US07570519B2
公开(公告)日：2009-08-04
申请号：US11230358
申请日：2005-09-19
申请人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
发明人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.
摘要翻译：在非易失性电子设备的编程期间，用于编程脉冲产生的方面包括提供可配置的电压序列发生器，用于在非易失性电子设备的编程算法的修改操作期间根据需要管理验证脉冲和脉冲验证切换，其中产生更有效的修改操作。以这种方式，可以容易地由微控制器管理的高度灵活的位序列生成，导致更短的代码长度，更快的执行时间以及在不同器件中的重用性。更具体地，引入完全兼容的电压序列生成，其可以应用于正被修改的闪存单元的端子，并且允许对脉冲验证和验证脉冲切换的有效且省时的管理。

10. 发明授权

US08553460B2 Method and system for program pulse generation during programming of nonvolatile electronic devices 有权
公开(公告)号：US08553460B2
公开(公告)日：2013-10-08
申请号：US13346979
申请日：2012-01-10
申请人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
发明人： Stefano Surico , Mirella Marsella , Monica Marziani , Mauro Chinosi
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/3454 , G11C16/3459
摘要： Aspects for program pulse generation during programming of nonvolatile electronic devices include providing a configurable voltage sequence generator to manage verify-pulse and pulse-verify switching as needed during modification operations of a programming algorithm for nonvolatile electronic devices, wherein more efficient modification operations result. In this manner, highly flexible bit sequence generation that can be easily managed by a microcontroller occurs, resulting in a shorter code length, a faster execution time, and ease of reuse in different devices. More particularly, fully compatible voltage sequence generation is introduced that can be applied on the terminals of the flash cells being modified and permits an efficient and time saving management of pulse-verify and verify-pulse switching.

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