专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07715255B2 Programmable chip enable and chip address in semiconductor memory 有权
标题翻译：半导体存储器中的可编程芯片使能和芯片地址
公开(公告)号：US07715255B2
公开(公告)日：2010-05-11
申请号：US11763287
申请日：2007-06-14
申请人： Loc Tu , Jian Chen , Alex Mak , Tien-Chien Kuo , Long Pham
发明人： Loc Tu , Jian Chen , Alex Mak , Tien-Chien Kuo , Long Pham
IPC分类号： G11C7/00
CPC分类号： H01L22/20 , H01L27/108 , H01L27/11 , H01L27/115 , H01L27/11524
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be readdressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用另一个可替代由焊盘键合提供的唯一芯片地址的可编程电路来读取一个或多个无缺陷存储器管芯。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

2. 发明授权

US07477545B2 Systems for programmable chip enable and chip address in semiconductor memory 有权
标题翻译：半导体存储器中可编程芯片使能和芯片地址的系统
公开(公告)号：US07477545B2
公开(公告)日：2009-01-13
申请号：US11763292
申请日：2007-06-14
申请人： Loc Tu , Jian Chen , Alex Mak , Tien-Chien Kuo , Long Pham
发明人： Loc Tu , Jian Chen , Alex Mak , Tien-Chien Kuo , Long Pham
IPC分类号： G11C16/04
CPC分类号： G11C29/88 , G11C5/04
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

3. 发明申请

US20130070530A1 HIGH ENDURANCE NON-VOLATILE STORAGE 有权
标题翻译：高耐久性非挥发性储存
公开(公告)号：US20130070530A1
公开(公告)日：2013-03-21
申请号：US13622045
申请日：2012-09-18
申请人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
发明人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

4. 发明申请

US20110126080A1 DATA CODING FOR IMPROVED ECC EFFICIENCY 有权
标题翻译：数据编码提高ECC效率
公开(公告)号：US20110126080A1
公开(公告)日：2011-05-26
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

5. 发明授权

US08473809B2 Data coding for improved ECC efficiency 有权
标题翻译：数据编码，提高ECC效率
公开(公告)号：US08473809B2
公开(公告)日：2013-06-25
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

6. 发明申请

US20120297111A1 Non-Volatile Memory And Method With Improved Data Scrambling 有权
标题翻译：非易失性存储器和改进的数据加扰方法
公开(公告)号：US20120297111A1
公开(公告)日：2012-11-22
申请号：US13109972
申请日：2011-05-17
申请人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
发明人： Jonathan Hsu , Chris Nga Yee Avila , Alexander Kwok-Tung Mak , Sergey Anatolievich Gorobets , Tien-Chien Kuo , Yee Lih Koh , Jun Wan
IPC分类号： G06F12/02
CPC分类号： G11C16/3427 , G06F12/1408 , G11C7/1006 , G11C7/1012
摘要： A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
摘要翻译：与存储器控制器协作的存储器件在将其存储在非易失性存储器单元阵列之前，使用所选择的加密密钥对每个数据单元进行加扰。这有助于减少由特定数据模式的重复和长期存储引起的程序干扰，用户读取干扰和浮动栅极到浮动栅极耦合。对于具有逻辑地址并用于存储在物理地址的给定页面的数据，从作为逻辑地址和物理地址的函数的有限序列中选择密钥。在块管理方案中，存储器阵列被组织成擦除块，物理地址是每个块中的相对页号。当逻辑地址分组为逻辑组并作为组操作并且每个组可存储到子块中时，物理地址是子块中的相对页号。

7. 发明授权

US08107298B2 Non-volatile memory with fast binary programming and reduced power consumption 有权
标题翻译：具有快速二进制编程和降低功耗的非易失性存储器
公开(公告)号：US08107298B2
公开(公告)日：2012-01-31
申请号：US12697017
申请日：2010-01-29
申请人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
发明人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3436 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642
摘要： In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.
摘要翻译：在非易失性存储系统中，通过最小化感测模块和管理电路之间的数据传输来减少执行编程操作所需的时间。感测模块与每个存储元件相关联。基于写入数据，对于要保持擦除状态的存储元件，将感测模块中的数据节点初始化为“0”，对于要编程为编程状态的存储元件，将“1”初始化为“1” 然后在编程完成时翻转到“0”。管理电路消除了访问写入数据以确定“0”是否表示完成编程的存储元件的需要。通过在一个程序验证迭代的验证阶段与下一个程序验证迭代的程序阶段之间保持位线电压高，也可以降低功耗。

8. 发明申请

US20140043898A1 Common Line Current for Program Level Determination in Flash Memory 有权
标题翻译：闪存中程序级确定的公共线电流
公开(公告)号：US20140043898A1
公开(公告)日：2014-02-13
申请号：US13569024
申请日：2012-08-07
申请人： Tien-Chien Kuo , Jonathan H. Huynh , Sung-En Wang
发明人： Tien-Chien Kuo , Jonathan H. Huynh , Sung-En Wang
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory.
摘要翻译：在存储随机数据的非易失性存储器阵列中，程序级别 - 存储在存储器单元群中的每个存储单元的状态数量是从在读取条件下通过存储器单元群体的总电流确定的，如在公共线，例如NAND闪存中的源线。

9. 发明授权

US08737125B2 Aggregating data latches for program level determination 有权
标题翻译：汇总数据锁存器进行程序级确定
公开(公告)号：US08737125B2
公开(公告)日：2014-05-27
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译：在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。

10. 发明申请

US20110188317A1 NON-VOLATILE MEMORY WITH FAST BINARY PROGRAMMING AND REDUCED POWER CONSUMPTION 有权
标题翻译：具有快速二进制编程和降低功耗的非易失性存储器
公开(公告)号：US20110188317A1
公开(公告)日：2011-08-04
申请号：US12697017
申请日：2010-01-29
申请人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
发明人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
IPC分类号： G11C16/06 , G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3436 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642
摘要： In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.
摘要翻译：在非易失性存储系统中，通过最小化感测模块和管理电路之间的数据传输来减少执行编程操作所需的时间。感测模块与每个存储元件相关联。基于写入数据，对于要保持擦除状态的存储元件，将感测模块中的数据节点初始化为“0”，对于要编程为编程状态的存储元件，将“1”初始化为“1” 然后在编程完成时翻转到“0”。管理电路不需要访问写入数据，以确定“0”是否表示完成编程的存储元件。通过在一个程序验证迭代的验证阶段与下一个程序验证迭代的程序阶段之间保持位线电压高，也可以降低功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式