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1. 发明申请

US20140043898A1 Common Line Current for Program Level Determination in Flash Memory 有权
标题翻译：闪存中程序级确定的公共线电流
公开(公告)号：US20140043898A1
公开(公告)日：2014-02-13
申请号：US13569024
申请日：2012-08-07
申请人： Tien-Chien Kuo , Jonathan H. Huynh , Sung-En Wang
发明人： Tien-Chien Kuo , Jonathan H. Huynh , Sung-En Wang
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—is determined from the total current passing through the population of memory cells under read conditions, as observed on a common line, for example a source line in NAND flash memory.
摘要翻译：在存储随机数据的非易失性存储器阵列中，程序级别 - 存储在存储器单元群中的每个存储单元的状态数量是从在读取条件下通过存储器单元群体的总电流确定的，如在公共线，例如NAND闪存中的源线。

2. 发明申请

US20130070530A1 HIGH ENDURANCE NON-VOLATILE STORAGE 有权
标题翻译：高耐久性非挥发性储存
公开(公告)号：US20130070530A1
公开(公告)日：2013-03-21
申请号：US13622045
申请日：2012-09-18
申请人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
发明人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

3. 发明授权

US08116139B2 Bit line stability detection 有权
标题翻译：位线稳定检测
公开(公告)号：US08116139B2
公开(公告)日：2012-02-14
申请号：US12697003
申请日：2010-01-29
申请人： Tien-chien Kuo , Man L. Mui
发明人： Tien-chien Kuo , Man L. Mui
IPC分类号： G11C11/34
CPC分类号： G11C5/14 , G11C7/10 , G11C16/06
摘要： A power supply and monitoring apparatus such as in a nonvolatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing operation, such as a read or verify operation, a discharge period is set in which a sense node of each sense module discharges into the associated bit line and string of non-volatile storage elements, when the string of non-volatile storage elements, is conductive. This discharge sinks current from the power supply, causing a perturbation. By sampling the power supply, a steady state condition can be detected from a rate of change. The steady state condition signals that the discharge period can be concluded and data can be latched from the sense node. The discharge period automatically adapts to different memory devices and environmental conditions.
摘要翻译：一种电源和监视装置，例如在非易失性存储器系统中。电源电路为大量的感测模块提供电力，每个感测模块与位线和一串非易失性存储元件相关联。在诸如读取或验证操作的感测操作期间，设置放电周期，其中每个感测模块的感测节点放电到相关联的位线和非易失性存储元件串中，当非易失性存储器串元件，是导电的。该放电从电源吸收电流，引起扰动。通过对电源进行采样，可以从变化率检测稳定状态。稳态条件指示放电周期可以结束，数据可以从感测节点锁存。放电周期自动适应不同的存储器件和环境条件。

4. 发明申请

US20110126080A1 DATA CODING FOR IMPROVED ECC EFFICIENCY 有权
标题翻译：数据编码提高ECC效率
公开(公告)号：US20110126080A1
公开(公告)日：2011-05-26
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F12/02 , H03M13/05 , G06F11/10
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

5. 发明申请

US20080311684A1 Programmable Chip Enable and Chip Address in Semiconductor Memory 有权
标题翻译：半导体存储器中的可编程芯片使能和芯片地址
公开(公告)号：US20080311684A1
公开(公告)日：2008-12-18
申请号：US11763287
申请日：2007-06-14
申请人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
发明人： Loc Tu , Jian Chen , Alex Mak , Tien-chien Kuo , Long Pham
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L27/108 , H01L27/11 , H01L27/115 , H01L27/11524
摘要： Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.
摘要翻译：存储器管芯具有可编程芯片使能电路，以允许在封装和/或可编程芯片地址电路之后禁止特定存储器管芯，以允许特定存储器管芯在封装之后被读取。在多芯片存储器封装中，可以通过可覆盖从控制器或主机设备接收的主芯片使能信号的可编程电路来禁止与存储器封装隔离的封装级测试失败的存储器管芯。为了提供连续的地址范围，可以使用替代由焊盘键合提供的唯一芯片地址的另一个可编程电路来重新寻址无缺陷存储器管芯中的一个或多个。封装后的存储器芯片也可以被独立于检测出错的存储器芯片而被读取。

6. 发明授权

US08737125B2 Aggregating data latches for program level determination 有权
标题翻译：汇总数据锁存器进行程序级确定
公开(公告)号：US08737125B2
公开(公告)日：2014-05-27
申请号：US13569008
申请日：2012-08-07
申请人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
发明人： Feng Pan , Tien-Chien Kuo , Jun Wan , Bo Lei
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/34
摘要： In a nonvolatile memory array that stores randomized data, the program level—the number of states per cell stored in a population of memory cells—may be determined from the aggregated results of a single read step. A circuit for aggregating binary results of a read step includes parallel transistors with control gates connected to the data latches holding the binary results, so that current flow through the combined transistors depends on the binary results.
摘要翻译：在存储随机化数据的非易失性存储器阵列中，可以从单个读取步骤的聚合结果确定程序级 - 存储在存储器单元群中的每个存储单元的状态数。用于聚合读取步骤的二进制结果的电路包括具有连接到保持二进制结果的数据锁存器的控制栅极的并行晶体管，使得通过组合晶体管的电流依赖于二进制结果。

7. 发明申请

US20140063961A1 WRITE DATA PRESERVATION FOR NON-VOLATILE STORAGE 有权
标题翻译：写入数据保存非易失性存储
公开(公告)号：US20140063961A1
公开(公告)日：2014-03-06
申请号：US13605583
申请日：2012-09-06
申请人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
发明人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.
摘要翻译：提供方法和非易失性存储系统用于在非易失性存储器的编程期间恢复数据。最初存储在一组锁存器中的程序数据可以通过两组锁存器的组合来保存。这两组锁存器也可用于在该程序数据的编程期间存储验证状态。可以通过对两组锁存器中的数据执行逻辑运算来恢复原始程序数据。例如，上页数据可以最初存储在一组锁存器中。当上位数据被编程时，该组锁存器和另一组锁存器用于存储相对于上位数据的验证状态。如果在保留上位页数据时发生程序错误，则可以通过对两组锁存器执行逻辑运算来恢复程序错误。

8. 发明授权

US08473809B2 Data coding for improved ECC efficiency 有权
标题翻译：数据编码，提高ECC效率
公开(公告)号：US08473809B2
公开(公告)日：2013-06-25
申请号：US12839237
申请日：2010-07-19
申请人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
发明人： Jun Wan , Alex Mak , Tien-Chien Kuo , Yan Li , Jian Chen
IPC分类号： G06F11/00 , G11C29/00 , G11C7/00
CPC分类号： G11C11/5642 , G11C11/5628 , G11C29/00
摘要： Non-volatile storage devices and techniques for operating non-volatile storage are described herein. One embodiment includes accessing “n” pages of data to be programmed into a group of non-volatile storage elements. The “n” pages are mapped to a data state for each of the non-volatile storage elements based on a coding scheme that evenly distributes read errors across the “n” pages of data. Each of the non-volatile storage elements in the group are programmed to a threshold voltage range based on the data states to which the plurality of pages have been mapped. The programming may include programming the “n” pages simultaneously. In one embodiment, mapping the plurality of pages is based on a coding scheme that distributes a significant failure mode (for example, program disturb errors) to a first of the pages and a significant failure mode (for example, data retention errors) to a second of the pages.
摘要翻译：本文描述了用于操作非易失性存储器的非易失性存储设备和技术。一个实施例包括访问要编程到一组非易失性存储元件中的“n”页数据。基于在“n”页数据上均匀分布读取错误的编码方案，将“n”个页映射到每个非易失性存储元件的数据状态。基于已经映射了多个页面的数据状态，组中的每个非易失性存储元件被编程到阈值电压范围。编程可以包括同时对“n”页进行编程。在一个实施例中，映射多个页面是基于将显着的故障模式（例如，程序干扰错误）分配给第一页面的编码方案和将重大故障模式（例如，数据保留错误）分配给第二页。

9. 发明授权

US08315093B2 Selective memory cell program and erase 有权
标题翻译：选择性存储单元程序和擦除
公开(公告)号：US08315093B2
公开(公告)日：2012-11-20
申请号：US13397428
申请日：2012-02-15
申请人： Yingda Dong , Tien-chien Kuo , Gerrit Jan Hemink
发明人： Yingda Dong , Tien-chien Kuo , Gerrit Jan Hemink
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/30 , G11C16/3418 , G11C2211/5641
摘要： Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.
摘要翻译：本文公开了用于编程存储器阵列以实现高编程/擦除周期耐久性的技术。在某些方面，只有选择的字线（WL）被编程，其他WL保持未编程。作为示例，只有偶数字线被编程，剩余的未编程的奇数WL。在所有偶数字线被编程并且数据块要用新数据编程之后，块被擦除。之后，只有奇数字线被编程。数据可以被传送到在擦除之前存储多个存储单元的位的块。在一个方面，数据以棋盘格式编程，其中编程了一些存储器单元，而其他存储器单元未被编程。之后，在擦除数据之后，棋盘格图案的以前未编程的部分被编程为剩余的单元未编程。

10. 发明申请

US20110188317A1 NON-VOLATILE MEMORY WITH FAST BINARY PROGRAMMING AND REDUCED POWER CONSUMPTION 有权
标题翻译：具有快速二进制编程和降低功耗的非易失性存储器
公开(公告)号：US20110188317A1
公开(公告)日：2011-08-04
申请号：US12697017
申请日：2010-01-29
申请人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
发明人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
IPC分类号： G11C16/06 , G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3436 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642
摘要： In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.
摘要翻译：在非易失性存储系统中，通过最小化感测模块和管理电路之间的数据传输来减少执行编程操作所需的时间。感测模块与每个存储元件相关联。基于写入数据，对于要保持擦除状态的存储元件，将感测模块中的数据节点初始化为“0”，对于要编程为编程状态的存储元件，将“1”初始化为“1” 然后在编程完成时翻转到“0”。管理电路不需要访问写入数据，以确定“0”是否表示完成编程的存储元件。通过在一个程序验证迭代的验证阶段与下一个程序验证迭代的程序阶段之间保持位线电压高，也可以降低功耗。

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