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1. 发明申请

US20130070530A1 HIGH ENDURANCE NON-VOLATILE STORAGE 有权
标题翻译：高耐久性非挥发性储存
公开(公告)号：US20130070530A1
公开(公告)日：2013-03-21
申请号：US13622045
申请日：2012-09-18
申请人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
发明人： Jian Chen , Sergei Gorobets , Steven Sprouse , Tien-Chien Kuo , Yan Li , Seungpil Lee , Alex Mak , Deepanshu Dutta , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C5/063 , G11C11/5628 , G11C2211/5641
摘要： A non-volatile storage system is disclosed that includes non-volatile memory cells designed for high endurance and lower retention than other non-volatile memory cells.
摘要翻译：公开了一种非易失性存储系统，其包括设计用于高耐久性和比其他非易失性存储器单元更低保持性的非易失性存储器单元。

2. 发明申请

US20130107628A1 Selective Word Line Erase In 3D Non-Volatile Memory 有权
公开(公告)号：US20130107628A1
公开(公告)日：2013-05-02
申请号：US13287343
申请日：2011-11-02
申请人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
发明人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
IPC分类号： G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/11582 , H01L29/7926
摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

3. 发明授权

US08897070B2 Selective word line erase in 3D non-volatile memory 有权
标题翻译： 3D非易失性存储器中的选择性字线擦除
公开(公告)号：US08897070B2
公开(公告)日：2014-11-25
申请号：US13287343
申请日：2011-11-02
申请人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
发明人： Yingda Dong , Alex Mak , Seungpil Lee , Johann Alsmeier
IPC分类号： G11C11/34 , G11C16/04 , G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/16 , H01L27/11582 , H01L29/7926
摘要： An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.
摘要翻译：用于3D堆叠存储器件的擦除处理允许擦除存储单元块的一部分。在一种方法中，在U形NAND串配置中，漏极或源极侧列中的存储单元被擦除。在另一种方法中，例如在U形或直的NAND串配置中，擦除存储器单元列的一部分中的存储单元，并且在擦除和未擦除的存储器单元之间提供虚拟存储单元。虚拟存储器单元可以在擦除存储器单元的任一侧（例如，高于和低于），或者在未擦除的存储器单元的任一侧上。虚拟存储单元不能存储用户数据，但是由于电容耦合，防止擦除的存储单元的阈值电压的降档改变未擦除的存储单元的阈值电压。

4. 发明申请

US20110222345A1 Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations 有权
标题翻译：非易失性存储器和方法，省电读取和程序验证操作
公开(公告)号：US20110222345A1
公开(公告)日：2011-09-15
申请号：US13114481
申请日：2011-05-24
申请人： Yan Li , Seungpil Lee , Siu Lung Chan
发明人： Yan Li , Seungpil Lee , Siu Lung Chan
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

5. 发明申请

US20060209592A1 Non-volatile memory and method with power-saving read and program-verify operations 有权
公开(公告)号：US20060209592A1
公开(公告)日：2006-09-21
申请号：US11083514
申请日：2005-03-16
申请人： Yan Li , Seungpil Lee , Siu Chan
发明人： Yan Li , Seungpil Lee , Siu Chan
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

6. 发明申请

US20120243332A1 Non-Volatile Memory and Method with Power-Saving Read and Program-Verify Operations 有权
标题翻译：非易失性存储器和省电读取和程序验证操作的方法
公开(公告)号：US20120243332A1
公开(公告)日：2012-09-27
申请号：US13430155
申请日：2012-03-26
申请人： Yan Li , Seungpil Lee , Siu Lung Chan
发明人： Yan Li , Seungpil Lee , Siu Lung Chan
IPC分类号： G11C16/10
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

7. 发明授权

US08154923B2 Non-volatile memory and method with power-saving read and program-verify operations 有权
标题翻译：具有省电读取和程序验证操作的非易失性存储器和方法
公开(公告)号：US08154923B2
公开(公告)日：2012-04-10
申请号：US13114481
申请日：2011-05-24
申请人： Yan Li , Seungpil Lee , Siu Lung Chan
发明人： Yan Li , Seungpil Lee , Siu Lung Chan
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

8. 发明授权

US07570513B2 Non-volatile memory and method with power-saving read and program-verify operations 有权
标题翻译：具有省电读取和程序验证操作的非易失性存储器和方法
公开(公告)号：US07570513B2
公开(公告)日：2009-08-04
申请号：US11534307
申请日：2006-09-22
申请人： Yan Li , Seungpil Lee , Siu Lung Chan
发明人： Yan Li , Seungpil Lee , Siu Lung Chan
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

9. 发明申请

US20070014161A1 Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations 有权
标题翻译：非易失性存储器和方法，省电读取和程序验证操作
公开(公告)号：US20070014161A1
公开(公告)日：2007-01-18
申请号：US11534297
申请日：2006-09-22
申请人： Yan Li , Seungpil Lee , Siu Chan
发明人： Yan Li , Seungpil Lee , Siu Chan
IPC分类号： G11C11/34 , G11C7/00 , G11C16/06
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.
摘要翻译：能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

10. 发明申请

US20070014156A1 Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations 有权
公开(公告)号：US20070014156A1
公开(公告)日：2007-01-18
申请号：US11534307
申请日：2006-09-22
申请人： Yan Li , Seungpil Lee , Siu Chan
发明人： Yan Li , Seungpil Lee , Siu Chan
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/5642 , G11C16/26 , G11C2211/5621
摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

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