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1. 发明申请

US20110188317A1 NON-VOLATILE MEMORY WITH FAST BINARY PROGRAMMING AND REDUCED POWER CONSUMPTION 有权
标题翻译：具有快速二进制编程和降低功耗的非易失性存储器
公开(公告)号：US20110188317A1
公开(公告)日：2011-08-04
申请号：US12697017
申请日：2010-01-29
申请人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
发明人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
IPC分类号： G11C16/06 , G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3436 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642
摘要： In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.
摘要翻译：在非易失性存储系统中，通过最小化感测模块和管理电路之间的数据传输来减少执行编程操作所需的时间。感测模块与每个存储元件相关联。基于写入数据，对于要保持擦除状态的存储元件，将感测模块中的数据节点初始化为“0”，对于要编程为编程状态的存储元件，将“1”初始化为“1” 然后在编程完成时翻转到“0”。管理电路不需要访问写入数据，以确定“0”是否表示完成编程的存储元件。通过在一个程序验证迭代的验证阶段与下一个程序验证迭代的程序阶段之间保持位线电压高，也可以降低功耗。

2. 发明申请

US20090237998A1 Adaptive Algorithm in Cache Operation with Dynamic Data Latch Requirements 有权
标题翻译：自适应算法在缓存操作中具有动态数据锁存要求
公开(公告)号：US20090237998A1
公开(公告)日：2009-09-24
申请号：US12051462
申请日：2008-03-19
申请人： Yan Li , Anne Pao-Ling Koh
发明人： Yan Li , Anne Pao-Ling Koh
IPC分类号： G11C16/04 , G11C16/06 , G11C7/00
CPC分类号： G11C16/10 , G06F12/0855 , G06F2212/2022 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C2207/2245 , G11C2211/5623 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation.
摘要翻译：非易失性存储器可以使用存储在相应的数据锁存器组中的第一组数据来执行一个或多个寻址页面的指定组上的第一操作（例如写入），并且还接收对还使用具有第二组数据的这些相应的数据锁存器中的一些的第二操作（例如读取）。在第一操作期间，当对应的每组的至少一个锁存器变得可用于第二操作时，存储器是否存在足够数量的对应的一组数据锁存器以在第一操作期间执行第二操作; 如果没有，则第二操作被延迟。当足够数量的锁存器变得可用时，存储器随后可以在第一操作期间执行第二操作; 并且如果响应于确定是否存在足够数量的对应的数据锁存器组来执行第二操作，则确定存在足够的数量，在第一操作期间执行第二操作。

3. 发明授权

US07009886B1 Integrated circuit memory device with bit line pre-charging based upon partial address decoding 有权
标题翻译：具有基于部分地址解码的位线预充电的集成电路存储器件
公开(公告)号：US07009886B1
公开(公告)日：2006-03-07
申请号：US10893809
申请日：2004-07-19
申请人： Neal Berger , George Chia-Jung Chang , Pearl Po-Yee Cheng , Anne Pao-Ling Koh
发明人： Neal Berger , George Chia-Jung Chang , Pearl Po-Yee Cheng , Anne Pao-Ling Koh
IPC分类号： G11C16/06
CPC分类号： G11C7/12
摘要： An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command. A decoder circuit receives the address signal and decodes the address signal as each of the plurality of bits is received and disconnects certain of the column lines to the pre-charge voltage in response to the decoding, and activates the sense amplifier circuit after all of the plurality of bits of the address signal are received.
摘要翻译：集成电路存储器件具有排列成多个行和列以及多条行线和多条列线的存储单元阵列。布置在同一行中的单元通过公共行线连接，并且排列在同一列中的单元通过公共列线连接。阵列中的每个单元由具有多个位的地址信号寻址。读出放大器电路可连接到阵列的多个列线中的一个或多个。地址输入端串联地址信号的多个位。响应读取命令，每列列线可连接到预充电电压。解码器电路接收地址信号并且在接收到多个比特中的每一个时对地址信号进行解码，并且响应于解码将某些列线断开到预充电电压，并且在全部接收地址信号的多个位。

4. 发明授权

US08730722B2 Saving of data in cases of word-line to word-line short in memory arrays 有权
标题翻译：在字线的情况下将数据保存到存储器阵列中的字线短路
公开(公告)号：US08730722B2
公开(公告)日：2014-05-20
申请号：US13411115
申请日：2012-03-02
申请人： Pao-Ling Koh , Tien-Chien Kuo
发明人： Pao-Ling Koh , Tien-Chien Kuo
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5685 , G11C29/025 , G11C2029/1202
摘要： Technique of operating a non-volatile memory are presented so that in case data that would otherwise be lost in the case of a word line to word line short is preserved. Before writing a word line, the data from a previously written adjacent is word line is read back and stored in data latches associated with the corresponding bit lines, but that are not being used for the data to be written. If a short occurs, as the data for both word lines is still in the latches, it can be written to a new location. This technique can also be incorporated into cache write operations and for a binary write operation inserted into a pause of a multi-state write.
摘要翻译：呈现操作非易失性存储器的技术，以便保留在字线短到字线短的情况下否则会丢失的数据。在写入字线之前，来自先前写入的相邻的数据是字线被读回并存储在与相应位线相关联的数据锁存器中，但是不被用于要被写入的数据。如果发生短路，由于两条字线的数据仍在锁存器中，因此可以将其写入新位置。这种技术也可以并入高速缓存写入操作和插入到多状态写入的暂停中的二进制写操作。

5. 发明申请

US20130229868A1 Saving of Data in Cases of Word-Line to Word-Line Short in Memory Arrays 有权
标题翻译：将字线数据保存到内存阵列中的字线短
公开(公告)号：US20130229868A1
公开(公告)日：2013-09-05
申请号：US13411115
申请日：2012-03-02
申请人： Pao-Ling Koh , Tien-Chien Kuo
发明人： Pao-Ling Koh , Tien-Chien Kuo
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5685 , G11C29/025 , G11C2029/1202
摘要： Technique of operating a non-volatile memory are presented so that in case data that would otherwise be lost in the case of a word line to word line short is preserved. Before writing a word line, the data from a previously written adjacent is word line is read back and stored in data latches associated with the corresponding bit lines, but that are not being used for the data to be written. If a short occurs, as the data for both word lines is still in the latches, it can be written to a new location. This technique can also be incorporated into cache write operations and for a binary write operation inserted into a pause of a multi-state write.
摘要翻译：呈现操作非易失性存储器的技术，以便保留在字线短到字线短的情况下否则会丢失的数据。在写入字线之前，来自先前写入的相邻的数据是字线被读回并存储在与相应位线相关联的数据锁存器中，但是不被用于要被写入的数据。如果发生短路，由于两条字线的数据仍在锁存器中，因此可以将其写入新位置。这种技术也可以并入高速缓存写入操作和插入到多状态写入的暂停中的二进制写操作。

6. 发明授权

US07027348B2 Power efficient read circuit for a serial output memory device and method 有权
公开(公告)号：US07027348B2
公开(公告)日：2006-04-11
申请号：US10921754
申请日：2004-08-17
申请人： Neal Berger , George Chia-Jung Chang , Pearl Po-Yee Cheng , Anne Pao-Ling Koh
发明人： Neal Berger , George Chia-Jung Chang , Pearl Po-Yee Cheng , Anne Pao-Ling Koh
IPC分类号： G11C8/00
CPC分类号： G11C7/08 , G11C7/1027 , G11C7/103
摘要： An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit. The control circuit receives a read command, and a clock signal, and in response to the read command activates a first plurality (j) of the plurality (k) of sense amplifiers (j

7. 发明申请

US20130219107A1 WRITE ABORT RECOVERY THROUGH INTERMEDIATE STATE SHIFTING 审中-公开
标题翻译：通过中间状态转换进行写入恢复
公开(公告)号：US20130219107A1
公开(公告)日：2013-08-22
申请号：US13401494
申请日：2012-02-21
申请人： Dana Lee , Pao-Ling Koh , Jianmin Huang , Gautam A. Dusija
发明人： Dana Lee , Pao-Ling Koh , Jianmin Huang , Gautam A. Dusija
IPC分类号： G06F12/02
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5648
摘要： A memory system or flash card may include a multi-level cell block with multiple states. Before the upper page is written, an intermediate state may be shifted to prevent or minimize overlapping of the states from the corresponding lower page. A write abort during the writing of the upper page will not result in a loss of data from the corresponding lower page.
摘要翻译：存储器系统或闪存卡可以包括具有多个状态的多级单元块。在写入上页之前，可以移动中间状态以防止或最小化来自相应下页的状态的重叠。在写入上一页时写入中止不会导致相应下页的数据丢失。

8. 发明授权

US07961512B2 Adaptive algorithm in cache operation with dynamic data latch requirements 有权
标题翻译：自适应算法在缓存操作中具有动态数据锁存要求
公开(公告)号：US07961512B2
公开(公告)日：2011-06-14
申请号：US12051462
申请日：2008-03-19
申请人： Yan Li , Anne Pao-Ling Koh
发明人： Yan Li , Anne Pao-Ling Koh
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G06F12/0855 , G06F2212/2022 , G11C7/1039 , G11C7/1078 , G11C7/1087 , G11C11/5628 , G11C11/5642 , G11C2207/2245 , G11C2211/5623 , G11C2211/5642 , G11C2211/5643
摘要： A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation.
摘要翻译：非易失性存储器可以使用存储在相应的数据锁存器组中的第一组数据来执行一个或多个寻址页面的指定组上的第一操作（例如写入），并且还接收对还使用具有第二组数据的这些相应的数据锁存器中的一些的第二操作（例如读取）。在第一操作期间，当对应的每组的至少一个锁存器变得可用于第二操作时，存储器是否存在足够数量的对应的一组数据锁存器以在第一操作期间执行第二操作; 如果没有，则第二操作被延迟。当足够数量的锁存器变得可用时，存储器随后可以在第一操作期间执行第二操作; 并且如果响应于确定是否存在足够数量的对应的数据锁存器组来执行第二操作，则确定存在足够的数量，在第一操作期间执行第二操作。

9. 发明授权

US08107298B2 Non-volatile memory with fast binary programming and reduced power consumption 有权
标题翻译：具有快速二进制编程和降低功耗的非易失性存储器
公开(公告)号：US08107298B2
公开(公告)日：2012-01-31
申请号：US12697017
申请日：2010-01-29
申请人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
发明人： Man L. Mui , Pao-Ling Koh , Tien-Chien Kuo , Khanh T. Nguyen
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3436 , G11C16/3459 , G11C16/3481 , G11C2211/5621 , G11C2211/5624 , G11C2211/5642
摘要： In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.
摘要翻译：在非易失性存储系统中，通过最小化感测模块和管理电路之间的数据传输来减少执行编程操作所需的时间。感测模块与每个存储元件相关联。基于写入数据，对于要保持擦除状态的存储元件，将感测模块中的数据节点初始化为“0”，对于要编程为编程状态的存储元件，将“1”初始化为“1” 然后在编程完成时翻转到“0”。管理电路消除了访问写入数据以确定“0”是否表示完成编程的存储元件的需要。通过在一个程序验证迭代的验证阶段与下一个程序验证迭代的程序阶段之间保持位线电压高，也可以降低功耗。

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