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1. 发明授权

US4501774A Process for the production of cobalt-containing magnetic iron oxide powder 失效
标题翻译：含钴磁性氧化铁粉末生产工艺
公开(公告)号：US4501774A
公开(公告)日：1985-02-26
申请号：US427537
申请日：1982-09-29
申请人： Kokichi Miyazawa , Kazuo Nakata , Tsuneo Ishikawa , Ichiro Honma , Masaharu Hirai , Makoto Ogasawara , Toshihiko Kawamura
发明人： Kokichi Miyazawa , Kazuo Nakata , Tsuneo Ishikawa , Ichiro Honma , Masaharu Hirai , Makoto Ogasawara , Toshihiko Kawamura
IPC分类号： C01G49/00 , G11B5/706 , B05D7/00
CPC分类号： G11B5/70684 , G11B5/70673 , Y10S428/90 , Y10T428/2991
摘要： A process is provided for coating the particle surfaces of a phosphor-containing magnetic iron oxide powder with a cobalt compound after subjecting said powder to an activation treatment with an aqueous alkaline and/or acidic medium. The cobalt-containing magnetic iron oxide powder obtained according to this process has excellent coercivity and thermal stability, and the magnetic tape produced by using said powder has not only high coercivity but also excellent squareness, orientability and remanent induction.
摘要翻译：提供了一种用于在用碱性和/或酸性介质水溶液处理所述粉末进行活化处理之后用钴化合物涂覆含磷光体的磁性氧化铁粉末的颗粒表面的方法。根据该方法获得的含钴磁性氧化铁粉末具有优异的矫顽力和热稳定性，并且通过使用所述粉末制造的磁带不仅具有高矫顽力，而且具有优异的矩形性，取向性和剩余感应性。

2. 发明授权

US06169324A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US06169324A
公开(公告)日：2001-01-02
申请号：US09413754
申请日：1999-10-06
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L2144
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

3. 发明授权

US5780882A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
公开(公告)号：US5780882A
公开(公告)日：1998-07-14
申请号：US456788
申请日：1995-06-01
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/02
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

4. 发明授权

US4331800A Process for producing aromatic polyesters having an increased degree of polymerization 失效
标题翻译：具有增加聚合度的芳族聚酯的制备方法
公开(公告)号：US4331800A
公开(公告)日：1982-05-25
申请号：US144036
申请日：1980-04-28
申请人： Hiroo Inata , Shunichi Matsumura , Makoto Ogasawara
发明人： Hiroo Inata , Shunichi Matsumura , Makoto Ogasawara
IPC分类号： C08G69/44 , C08G63/68
CPC分类号： C08G69/44
摘要： A process for producing an aromatic polyester having an increased degree of polymerization, which comprises reacting a substantially linear, fiber forming aromatic polyester containing terminal hydroxyl groups and having an aromatic dicarboxylic acid as a main acid component at an elevated temperature with a bis-cyclic imino ether compound of the formula [I] such as 2,2'-bis(2-oxazoline), 2,2'-bis(5,6-dihydro-4H-1,3-oxadine) thereby bonding the molecular chains of the aromatic polyester to each other by the terminal carboxyl groups thereof to rapidly form said aromatic polyester having an increased degree of polymerization.Said reaction can be carried out under atmospheric or elevated pressure.According to the process, an aromatic polyester having a low terminal caboxyl concentration and an increased degree of polymerization can be obtained.
摘要翻译：一种具有增加聚合度的芳族聚酯的制备方法，该方法包括使具有末端羟基并且具有芳族二羧酸作为主要酸成分的基本上直链的形成纤维的芳族聚酯在升高的温度下与双环亚氨基醚化合物，如2,2'-双（2-恶唑啉），2,2'-双（5,6-二氢-4H-1,3-恶嗪等），由此将分子链芳族聚酯通过其末端羧基彼此之间，以快速形成具有增加的聚合度的所述芳族聚酯。所述反应可以在大气压或高压下进行。根据该方法，可以得到具有低端甲氧基浓度和增加聚合度的芳族聚酯。

5. 发明授权

US4196066A Cured aromatic polyester composition and process for its production 失效
标题翻译：固化芳香族聚酯组合物及其生产工艺
公开(公告)号：US4196066A
公开(公告)日：1980-04-01
申请号：US920834
申请日：1978-06-30
申请人： Hiroo Inata , Makoto Ogasawara , Tsuto Morinaga , Akihiro Norike
发明人： Hiroo Inata , Makoto Ogasawara , Tsuto Morinaga , Akihiro Norike
IPC分类号： C08G63/58 , C08G63/91 , C08L67/06 , C08F8/00 , C08G18/00
CPC分类号： C08L67/06 , C08G63/58 , C08G63/916
摘要： A cured or uncured linear aromatic polyester composition melt-blended and composed of(A) 100 parts by weight of a saturated linear aromatic polyester in which at least 70 mole % of the acid component consists of an aromatic dicarboxylic acid, and(B) 0.1 to 50 parts by weight of a reactive compound which is solid at room temperature or is a liquid having a boiling point of at least 200.degree. C. under atmospheric pressure, and which contains in its molecule at least one aliphatic unsaturated group substantially non-reactive with the polyester (A) and the aliphatic unsaturated group of the reactive compound (B) under conditions of melt-blending with the polyester (A) and at least one epoxy group reactive with the polyester (A) under the melt-blending conditions. The cured linear aromatic polyester composition can be prepared by extruding the uncured linear aromatic polyester composition under melting conditions, and subjecting the resulting extrudate to a curing treatment.
摘要翻译：固化或未固化的线性芳族聚酯组合物熔融共混并由（A）100重量份的饱和直链芳族聚酯组成，其中至少70摩尔％的酸组分由芳族二羧酸组成，和（B）0.1 至50重量份在室温下为固体的反应性化合物或在大气压下为沸点为至少200℃的液体，并且其在其分子中含有至少一个基本上不反应的脂族不饱和基团与聚酯（A）的熔融共混条件下的聚酯（A）和反应性化合物（B）的脂肪族不饱和基团和至少一种与聚酯（A）反应的环氧基团在熔融共混条件下进行。固化的线性芳族聚酯组合物可以通过在熔融条件下挤出未固化的线性芳族聚酯组合物并将所得挤出物进行固化处理来制备。

6. 发明授权

US06949387B2 Method of designing a semiconductor device 失效
标题翻译：设计半导体器件的方法
公开(公告)号：US06949387B2
公开(公告)日：2005-09-27
申请号：US10626718
申请日：2003-07-25
申请人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L21/66
CPC分类号： H01L21/76205 , H01L21/76202 , H01L27/0802
摘要： A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.
摘要翻译：提供了一种半导体器件的技术，其包括在器件形成区域上形成电路区域和半导体衬底上的器件隔离区域，器件隔离区域的宽度与其相邻电路区域的宽度的比率被设置为2至还提供了一种设计方法，包括进行测量，例如衬垫氧化膜和氮化物膜的厚度，氮化物膜的内部应力，器件形成和隔离区域的宽度，蚀刻部分的深度的用于在器件隔离区域中形成沟槽的氮化物膜，由于热氧化而在沟槽附近进行导电应力分析，以及与器件形成区域的宽度和不引导的器件隔离区域的设定值发生脱位。

7. 发明授权

US06894334B2 Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US06894334B2
公开(公告)日：2005-05-17
申请号：US10376329
申请日：2003-03-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

8. 发明授权

US06573546B2 Semiconductor integrated circuit device and process for manufacturing the same 有权
公开(公告)号：US06573546B2
公开(公告)日：2003-06-03
申请号：US09922673
申请日：2001-08-07
申请人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
发明人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10894
摘要： A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

9. 发明授权

US06548847B2 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM 失效
标题翻译：具有通过连接孔暴露的第一布线的半导体集成电路器件，连接孔中的过渡金属膜和铝导线之间的过渡金属膜以及铝导线和过渡金属膜之间的过渡金属氮化物膜
公开(公告)号：US06548847B2
公开(公告)日：2003-04-15
申请号：US09899921
申请日：2001-07-09
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L2976
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

10. 发明授权

US5889312A Semiconductor device having circuit element in stress gradient region by film for isolation and method of manufacturing the same 失效
标题翻译：具有用于隔离膜的应力梯度区域中的电路元件的半导体器件及其制造方法
公开(公告)号：US5889312A
公开(公告)日：1999-03-30
申请号：US890997
申请日：1997-07-10
申请人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L3/22 , H01L21/265
CPC分类号： H01L21/76202 , H01L27/0802
摘要： A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.
摘要翻译：半导体器件包括用于隔离的热氧化膜，半导体区域，其成为元件形成区域，其周边被半导体区域中的氧化物膜和扩散电阻层包围，并且提供用于控制起始的扩散电阻器的电阻值变化的结构在形成用于隔离的氧化膜时产生的应力。最靠近扩散层的热氧化膜的较长侧的端部与热氧化膜的端部之间的距离彼此分开由半导体区域中的应力分布确定的预定值或至少4 从热氧化膜的端部到半导体区域的应力分布（梯度）形成区域形成的扩散层部的纵向方向平行于应力梯度的形成方向，电阻值分布形成为平行于从热氧化膜的端部到半导体区域中的应力分布形成区域形成的扩散层中的应力梯度。

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