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1. 发明授权

US4662057A Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US4662057A
公开(公告)日：1987-05-05
申请号：US759441
申请日：1985-07-26
申请人： Hideki Yasuoka , Yasunobu Tanizaki , Akira Muramatsu , Norio Anzai
发明人： Hideki Yasuoka , Yasunobu Tanizaki , Akira Muramatsu , Norio Anzai
IPC分类号： H01L29/78 , H01L21/76 , H01L21/8249 , H01L27/00 , H01L27/06 , H01L27/092 , H01L21/425
CPC分类号： H01L21/76 , H01L21/8249 , H01L27/0623 , H01L27/092
摘要： The present invention relates to a Bi-CMOS.IC, characterized by comprising a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type which is epitaxially grown on one major surface of said semiconductor substrate and which is electrically isolated into a plurality of semiconductor island regions by a thick surface oxide film formed by local oxidation and a semiconductor diffused layer of the first conductivity type formed between said oxide film and said substrate; a bipolar type semiconductor element being formed in one of said island regions, while CMOS type semiconductor elements are formed in the other island regions; the thick surface oxide film formed by the local oxidation being included between a base region and a collector contact region within said one island region formed with said bipolar type semiconductor element, while gate electrodes made of a semiconductor are disposed over said other island regions formed with said CMOS type semiconductor elements.
摘要翻译：本发明涉及一种Bi-CMOS.IC，其特征在于包括第一导电类型的半导体衬底和第二导电类型的半导体层，其外延生长在所述半导体衬底的一个主表面上并且被电隔离通过局部氧化形成的厚表面氧化膜和形成在所述氧化膜和所述衬底之间的第一导电类型的半导体扩散层而形成多个半导体岛区域; 在所述岛状区域之一上形成双极型半导体元件，在其他岛状区域形成有CMOS型半导体元件; 由局部氧化形成的厚表面氧化膜包括在形成有所述双极型半导体元件的所述一个岛状区域内的基极区域与集电极接触区域之间，而由半导体制成的栅极电极设置在形成有所述CMOS型半导体元件。

2. 发明授权

US5889312A Semiconductor device having circuit element in stress gradient region by film for isolation and method of manufacturing the same 失效
标题翻译：具有用于隔离膜的应力梯度区域中的电路元件的半导体器件及其制造方法
公开(公告)号：US5889312A
公开(公告)日：1999-03-30
申请号：US890997
申请日：1997-07-10
申请人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
发明人： Hideo Miura , Yasunobu Tanizaki , Eiji Wakimoto , Shinji Sakata , Makoto Ogasawara , Hiroo Masuda , Jun Murata , Noriaki Okamoto
IPC分类号： H01L21/762 , H01L27/08 , H01L3/22 , H01L21/265
CPC分类号： H01L21/76202 , H01L27/0802
摘要： A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.
摘要翻译：半导体器件包括用于隔离的热氧化膜，半导体区域，其成为元件形成区域，其周边被半导体区域中的氧化物膜和扩散电阻层包围，并且提供用于控制起始的扩散电阻器的电阻值变化的结构在形成用于隔离的氧化膜时产生的应力。最靠近扩散层的热氧化膜的较长侧的端部与热氧化膜的端部之间的距离彼此分开由半导体区域中的应力分布确定的预定值或至少4 从热氧化膜的端部到半导体区域的应力分布（梯度）形成区域形成的扩散层部的纵向方向平行于应力梯度的形成方向，电阻值分布形成为平行于从热氧化膜的端部到半导体区域中的应力分布形成区域形成的扩散层中的应力梯度。

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