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1. 发明授权

US5918246A Apparatus and method for prefetching data based on information contained in a compiler generated program map 失效
标题翻译：基于编译器生成的程序映射中包含的信息来预取数据的装置和方法
公开(公告)号：US5918246A
公开(公告)日：1999-06-29
申请号：US788870
申请日：1997-01-23
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F9/45 , G06F12/08 , G06F12/00 , G06F9/38 , G06F13/00
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/6028
摘要： An apparatus and method for pre-loading a cache memory based on information contained in a compiler generated program map are disclosed. The program map is generated by the compiler at the time source code is compiled into object code. For each application program, the user would have this program map stored with the object file. At the beginning of the program execution cycle, the operating system will determine whether or not a program map exists for the application. If a program map exists, the operating system will load the program map into an area of RAM designated as the program map random access memory (RAM). The program map will be used to pre-load the cache with the appropriate data and instructions for the central processing unit (CPU) to process. The program mapping would be the address location of each jump/branch target that the CPU might encounter during the execution cycle. Each of these locations represent a starting point for a new code sequence. At the start of the map will be an identifier field to mark the start of the map. The next field in the program map will provide the entry point of the starting address of the application program. If a particular application program does not have a program map, the program and cache operation will remain unchanged. This feature provides backwards compatibility with existing application programs.
摘要翻译：公开了一种基于编译器生成的程序映射中包含的信息来预加载高速缓冲存储器的装置和方法。程序地图由编译器在源代码被编译成目标代码时生成。对于每个应用程序，用户将该目录文件存储该程序映射。在程序执行周期开始时，操作系统将确定应用程序是否存在程序映射。如果存在程序映射，则操作系统将程序映射加载到指定为程序映射随机存取存储器（RAM）的RAM区域中。程序地图将用于预先加载高速缓存，并具有相应的数据和指令，供中央处理单元（CPU）处理。程序映射将是执行周期中CPU可能遇到的每个跳转/转移目标的地址位置。这些位置中的每一个代表新代码序列的起始点。在地图的开始，将是一个标识符字段来标记地图的开始。程序地图中的下一个字段将提供应用程序起始地址的入口点。如果特定的应用程序没有程序映射，程序和缓存操作将保持不变。此功能提供与现有应用程序的向后兼容性。

2. 发明授权

US6026471A Anticipating cache memory loader and method 失效
标题翻译：预测缓存内存加载器和方法
公开(公告)号：US6026471A
公开(公告)日：2000-02-15
申请号：US751468
申请日：1996-11-19
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F9/46 , G06F12/08 , G06F12/10 , G06F17/12
CPC分类号： G06F12/0862 , G06F9/461 , G06F2212/6024
摘要： According to the present invention, an anticipating cache memory loader is provided to "pre-load" the cache with the data and instructions most likely to be needed by the CPU once the currently executing task is completed or interrupted. The data and instructions most likely to be needed after the currently executing task is completed or executed is the same data and instructions that were loaded into the cache at the time the next scheduled task was last preempted or interrupted. By creating and storing an index to the contents of the cache for various tasks at the point in time the tasks are interrupted, the data and instructions previously swapped out of the cache can be retrieved from main memory and restored to the cache when needed. By using available bandwidth to pre-load the cache for the next scheduled task, the CPU can begin processing the next scheduled task more quickly and efficiently than if the present invention were not utilized. Using the present invention, CPU stalls will be reduced because the CPU will operate more efficiently without waiting for excessive periods of time for the cache to be loaded with relevant data and instructions.
摘要翻译：根据本发明，提供一种预期的高速缓存存储器加载器，用于在当前执行的任务完成或中断之后，用CPU最有可能需要的数据和指令来“预加载”高速缓存。在完成或执行当前执行任务之后最可能需要的数据和指令是在下一个计划任务最后被抢占或中断时加载到缓存中的相同数据和指令。通过在任务中断的时间点为各种任务创建和存储索引到高速缓存的内容，可以从主存储器中检索先前从高速缓存交换的数据和指令，并在需要时将其还原到高速缓存。通过使用可用带宽来预加载用于下一个计划任务的高速缓存，与不利用本发明相比，CPU可以更快速和有效地开始处理下一个计划的任务。使用本发明，CPU停止将被减少，因为CPU将更有效地操作而不用等待超时间段来缓存相关数据和指令。

3. 发明授权

US06345362B1 Managing Vt for reduced power using a status table 有权
标题翻译：使用状态表管理Vt降低功耗
公开(公告)号：US06345362B1
公开(公告)日：2002-02-05
申请号：US09287173
申请日：1999-04-06
申请人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
发明人： Claude Louis Bertin , Alvar Antonio Dean , Kenneth Joseph Goodnow , Scott Whitney Gould , Wilbur David Pricer , William Robert Tonti , Sebastian Theodore Ventrone
IPC分类号： G06F132
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F9/3867 , G06F9/3869 , Y02D10/126 , Y02D10/171
摘要： An integrated circuit includes a CPU, a power management unit and plural functional units each dedicated to executing different functions. The power management unit controls the threshold voltage of the different functional units to optimize power/performance operation of the circuit and intelligent power management control responds to the instruction stream and decodes each instruction in turn. This information identifies which of the functional units are required for the particular instruction and by comparing that information to power status, the intelligent power control determines whether the functional units required to execute the command are at the optimum power level. If they are, the command is allowed to proceed, otherwise the intelligent power control either stalls the instruction sequence or modifies process speed.
摘要翻译：集成电路包括CPU，电源管理单元和专用于执行不同功能的多个功能单元。电源管理单元控制不同功能单元的阈值电压，以优化电路的功率/性能运行，智能电源管理控制响应指令流并依次对每条指令进行解码。该信息识别特定指令需要哪个功能单元，并且通过将该信息与功率状态进行比较，智能功率控制确定执行命令所需的功能单元是否处于最佳功率级。如果是，则允许该命令继续进行，否则智能功率控制将停止指令序列或修改处理速度。

4. 发明授权

US6141351A Radio frequency bus for broadband microprocessor communications 失效
标题翻译：无线电频率总线用于宽带微处理器通信
公开(公告)号：US6141351A
公开(公告)日：2000-10-31
申请号：US770355
申请日：1996-12-20
申请人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/403
CPC分类号： H04Q11/0478 , H04L2012/5613 , H04L2012/5679
摘要： Disclosed is a system for providing broader bandwidth in microprocessor bus, board and system designs. Broader bandwidth is achieved by dividing the full spectrum of frequencies available into discrete bandwidth packages, much like radio communications. The system includes a bus that is controlled by a traffic controller that polls for communication requests on the bus and then allocates bandwidth among the devices submitting such requests.
摘要翻译：公开了一种在微处理器总线，板和系统设计中提供更宽带宽的系统。通过将可用的全部频谱划分为离散带宽包，实现更宽带宽，就像无线电通信一样。该系统包括由流量控制器控制的总线，其轮询总线上的通信请求，然后在提交这样的请求的设备之间分配带宽。

5. 发明授权

US5832284A Self regulating temperature/performance/voltage scheme for micros (X86) 失效
公开(公告)号：US5832284A
公开(公告)日：1998-11-03
申请号：US772706
申请日：1996-12-23
申请人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F1/08 , G06F1/20 , G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02B60/1217 , Y02B60/1285
摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

6. 发明授权

US6119241A Self regulating temperature/performance/voltage scheme for micros (X86) 有权
标题翻译：微调自适应温度/性能/电压方案（X86）
公开(公告)号：US6119241A
公开(公告)日：2000-09-12
申请号：US183342
申请日：1998-10-30
申请人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F1/08 , G06F1/20 , G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02B60/1217 , Y02B60/1285
摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.
摘要翻译：一种处理器，通过使用包括电压，时钟和由处理器或其系统执行的操作的变量的层次来机会地优化性能。本发明通过定义各种状态来实现性能优化，目的在于处理器执行单元正在运行时处理器处于加速电压和时钟的最佳性能状态。状态由逻辑网络基于由温度传感器和性能控制提供的信息来选择。逻辑网络可以设想为一个UP-DOWN计数器。根据条件，计数器可以向上或向下进入状态“梯子”。

7. 发明授权

US5793815A Calibrated multi-voltage level signal transmission system 失效
标题翻译：校准多电平电平信号传输系统
公开(公告)号：US5793815A
公开(公告)日：1998-08-11
申请号：US766240
申请日：1996-12-13
申请人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sabastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sabastian Theodore Ventrone
IPC分类号： H04L1/24 , H04L25/34 , H04L25/49
CPC分类号： H04L1/242
摘要： A calibrated multi-voltage level system is disclosed having a network of devices, including a first and a second device. The first device comprises a processor for generating data, an encoding unit for encoding the data into a first data signal having multiple voltage levels, and a transmitting unit for transmitting the encoded data signal to the second device. The first device also comprises a calibration unit for sending a first calibration signal to the second device, and for storing a second calibration signal from the second device; and an adaptation unit for correcting the second data signal from the second device with the stored second calibration signal.
摘要翻译：公开了具有包括第一和第二设备的设备网络的校准多电压电平系统。第一设备包括用于产生数据的处理器，用于将数据编码为具有多个电压电平的第一数据信号的编码单元，以及用于将编码数据信号发送到第二设备的发送单元。第一设备还包括用于向第二设备发送第一校准信号并用于存储来自第二设备的第二校准信号的校准单元; 以及适配单元，用于利用所存储的第二校准信号来校正来自第二设备的第二数据信号。

8. 发明授权

US06453431B1 System technique for detecting soft errors in statically coupled CMOS logic 失效
标题翻译：用于检测静态耦合CMOS逻辑中的软错误的系统技术
公开(公告)号：US06453431B1
公开(公告)日：2002-09-17
申请号：US09346509
申请日：1999-07-01
申请人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
IPC分类号： G06K504
CPC分类号： G11C5/005 , G06F11/00
摘要： Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.
摘要翻译：用于检测由于原子事件或其他非循环噪声源引起的逻辑电路中的错误瞬变的电路包括耦合到数据线的第一电路，用于感测在第一时间点（T1）的数据线上的第一信号，以及第二电路耦合到数据线，用于在第二时间点（T2）感测数据线上的第一信号，使得T1和T2之间的时间差足够小，使得第一信号在不存在的情况下仍然存在于数据线上的扰动事件，并且使得T1和T2之间的时间差足够大，使得任何这样的扰动事件被解决。耦合到第一和第二电路的比较电路比较第一和第二电路对第一信号的感测，并且响应于非比较而产生误差信号。

9. 发明授权

US6091273A Voltage limiting circuit for fuse technology 失效
标题翻译：保险丝技术限压电路
公开(公告)号：US6091273A
公开(公告)日：2000-07-18
申请号：US914857
申请日：1997-08-19
申请人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Daniel Charles Edelstein , William Alan Klaasen , Wilbur David Pricer
IPC分类号： G11C17/18 , H03K17/687 , H03L5/00
CPC分类号： H03K17/6872 , G11C17/18
摘要： A voltage limiting circuit for fuse technology. The voltage limiting circuit is coupled to the two terminals. The voltage limiting circuit is responsive to a fuse blow through a low impedance sensing circuit, and then minimizes the voltage across the fuse gap that is created by the fuse blow. Thus, the invention prevents dendritic growth and corrosion in copper or similar types of fuses.
摘要翻译：一种用于保险丝技术的限压电路。电压限制电路耦合到两个端子。电压限制电路响应于通过低阻抗感测电路的保险丝熔断，然后使由保险丝熔断产生的熔丝间隙上的电压最小化。因此，本发明防止了铜或类似类型的保险丝中的树枝状生长和腐蚀。

10. 发明授权

US5841309A Low voltage input buffer for asymmetrical logic signals 失效
标题翻译：用于非对称逻辑信号的低电压输入缓冲器
公开(公告)号：US5841309A
公开(公告)日：1998-11-24
申请号：US769976
申请日：1996-12-19
申请人： Anthony Richard Bonaccio , Wilbur David Pricer
发明人： Anthony Richard Bonaccio , Wilbur David Pricer
IPC分类号： H03K19/00 , H03K19/0185 , H03K17/16
CPC分类号： H03K19/018521 , H03K19/0027
摘要： An input buffer circuit has a switching point accurately set according to the input logic level, even when the input buffer circuit has a low supply voltage. The switching point is set according to an internal reference voltage of equal magnitude to the desired switching point that is applied to a current source. The current source accurately sources (or sinks) a current matching the current flowing in an input inverter when the input logic level substantially equals the reference voltage. At that point, the voltage at the output of the input inverter is substantially equal one half of the supply voltage. When the input logic level is slightly below or above the reference voltage, the output of the input inverter is near the supply or ground rail, respectively. Hysteresis is added to compensate for noise that may exist on the input logic signal.
摘要翻译：输入缓冲电路具有根据输入逻辑电平精确设定的切换点，即使输入缓冲电路具有低电源电压。切换点根据与施加到电流源的所需切换点相等的内部参考电压来设置。当输入逻辑电平基本上等于参考电压时，电流源精确地源（或吸收）与输入反相器中流动的电流匹配的电流。此时，输入逆变器输出端的电压基本上等于电源电压的一半。当输入逻辑电平略低于或高于参考电压时，输入反相器的输出分别靠近电源或接地导轨。添加滞后以补偿输入逻辑信号可能存在的噪声。

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