专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5793815A Calibrated multi-voltage level signal transmission system 失效
标题翻译：校准多电平电平信号传输系统
公开(公告)号：US5793815A
公开(公告)日：1998-08-11
申请号：US766240
申请日：1996-12-13
申请人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sabastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sabastian Theodore Ventrone
IPC分类号： H04L1/24 , H04L25/34 , H04L25/49
CPC分类号： H04L1/242
摘要： A calibrated multi-voltage level system is disclosed having a network of devices, including a first and a second device. The first device comprises a processor for generating data, an encoding unit for encoding the data into a first data signal having multiple voltage levels, and a transmitting unit for transmitting the encoded data signal to the second device. The first device also comprises a calibration unit for sending a first calibration signal to the second device, and for storing a second calibration signal from the second device; and an adaptation unit for correcting the second data signal from the second device with the stored second calibration signal.
摘要翻译：公开了具有包括第一和第二设备的设备网络的校准多电压电平系统。第一设备包括用于产生数据的处理器，用于将数据编码为具有多个电压电平的第一数据信号的编码单元，以及用于将编码数据信号发送到第二设备的发送单元。第一设备还包括用于向第二设备发送第一校准信号并用于存储来自第二设备的第二校准信号的校准单元; 以及适配单元，用于利用所存储的第二校准信号来校正来自第二设备的第二数据信号。

2. 发明授权

US6141351A Radio frequency bus for broadband microprocessor communications 失效
标题翻译：无线电频率总线用于宽带微处理器通信
公开(公告)号：US6141351A
公开(公告)日：2000-10-31
申请号：US770355
申请日：1996-12-20
申请人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/403
CPC分类号： H04Q11/0478 , H04L2012/5613 , H04L2012/5679
摘要： Disclosed is a system for providing broader bandwidth in microprocessor bus, board and system designs. Broader bandwidth is achieved by dividing the full spectrum of frequencies available into discrete bandwidth packages, much like radio communications. The system includes a bus that is controlled by a traffic controller that polls for communication requests on the bus and then allocates bandwidth among the devices submitting such requests.
摘要翻译：公开了一种在微处理器总线，板和系统设计中提供更宽带宽的系统。通过将可用的全部频谱划分为离散带宽包，实现更宽带宽，就像无线电通信一样。该系统包括由流量控制器控制的总线，其轮询总线上的通信请求，然后在提交这样的请求的设备之间分配带宽。

3. 发明授权

US5767728A Noise tolerant CMOS inverter circuit having a resistive bias 失效
标题翻译：具有电阻偏置的耐噪声CMOS反相器电路
公开(公告)号：US5767728A
公开(公告)日：1998-06-16
申请号：US711424
申请日：1996-09-05
申请人： Michel Salib Michail , Wilbur David Pricer
发明人： Michel Salib Michail , Wilbur David Pricer
IPC分类号： H03K19/003 , H03K17/04 , H03K17/687
CPC分类号： H03K19/00361
摘要： A CMOS inverter circuit having a resistive bias device is disclosed. The CMOS inverter circuit comprises a pair of inverter transistors for receiving an input signal. At least one pair of compensating transistors is coupled to the inverter transistors for providing nonlinearity to the input signal. An inverter, coupled to the drains of the inverter transistors at a first node, receives the nonlinear signal as an input. The resistive bias device, coupled to the output of the inverter and to the compensation transistors, provides adjustable reference voltages to the compensation transistors, which allow for an improved noise immunity and high transition gain. The output, taken from the first node, provides for an improvement in the performance of the circuit.
摘要翻译：公开了一种具有电阻偏置装置的CMOS反相器电路。 CMOS反相器电路包括用于接收输入信号的一对反相晶体管。至少一对补偿晶体管耦合到反相器晶体管，以向输入信号提供非线性。耦合到第一节点处的反相器晶体管的漏极的反相器接收非线性信号作为输入。耦合到反相器的输出端和补偿晶体管的电阻偏置装置向补偿晶体管提供可调参考电压，这允许改善的抗干扰性和高跃迁增益。从第一个节点取得的输出提供了电路性能的改进。

4. 发明授权

US5832284A Self regulating temperature/performance/voltage scheme for micros (X86) 失效
公开(公告)号：US5832284A
公开(公告)日：1998-11-03
申请号：US772706
申请日：1996-12-23
申请人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F1/08 , G06F1/20 , G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02B60/1217 , Y02B60/1285
摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.

5. 发明授权

US5760649A Buffer amplifier with output non-linearity compensation and adjustable gain 失效
标题翻译：具有输出非线性补偿和可调增益的缓冲放大器
公开(公告)号：US5760649A
公开(公告)日：1998-06-02
申请号：US753139
申请日：1996-11-20
申请人： Michel Salib Michail , Wilbur David Pricer
发明人： Michel Salib Michail , Wilbur David Pricer
IPC分类号： H03F1/32 , H03F3/30
CPC分类号： H03F1/3217
摘要： According to the preferred embodiment, a buffer amplifier is provided that provides improved linearity while providing increased control over the gain without unduly limiting the amplifier frequency response. The amplifier preferably includes a series pair of transistors with their gates connected to the amplifier input and their drains connected to the amplifier output. The amplifier further includes a pair of feedback transistors connected in series with the series pair. The gates of the feedback transistors are connected to the amplifier output through a pair of feedback networks. Each network includes at least one impedance element. The impedance elements are preferably selected to maximize the linearity of the amplifier response. Furthermore, the impedance elements can be selected to modify the gain of the amplifier, increasing the amplifier gain if needed.
摘要翻译：根据优选实施例，提供一种缓冲放大器，其提供改进的线性度，同时提供对增益的增加的控制，而不会过度地限制放大器频率响应。放大器优选地包括一对串联的晶体管，其栅极连接到放大器输入端，并且其漏极连接到放大器输出端。放大器还包括与串联对串联的一对反馈晶体管。反馈晶体管的栅极通过一对反馈网络连接到放大器输出端。每个网络包括至少一个阻抗元件。优选地选择阻抗元件以使放大器响应的线性最大化。此外，可以选择阻抗元件来修改放大器的增益，如果需要，增加放大器增益。

6. 发明授权

US6119241A Self regulating temperature/performance/voltage scheme for micros (X86) 有权
标题翻译：微调自适应温度/性能/电压方案（X86）
公开(公告)号：US6119241A
公开(公告)日：2000-09-12
申请号：US183342
申请日：1998-10-30
申请人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Michel Salib Michail , Wilbur David Pricer , Sebastian Theodore Ventrone
IPC分类号： G06F1/08 , G06F1/20 , G06F1/32 , G06F1/26
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02B60/1217 , Y02B60/1285
摘要： A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.
摘要翻译：一种处理器，通过使用包括电压，时钟和由处理器或其系统执行的操作的变量的层次来机会地优化性能。本发明通过定义各种状态来实现性能优化，目的在于处理器执行单元正在运行时处理器处于加速电压和时钟的最佳性能状态。状态由逻辑网络基于由温度传感器和性能控制提供的信息来选择。逻辑网络可以设想为一个UP-DOWN计数器。根据条件，计数器可以向上或向下进入状态“梯子”。

7. 发明授权

US5949265A Soft latch circuit having sharp-cornered hysteresis characteristics 失效
标题翻译：软锁存电路具有尖角滞后特性
公开(公告)号：US5949265A
公开(公告)日：1999-09-07
申请号：US961928
申请日：1997-10-31
申请人： John Anthony Bracchitta , Michel Salib Michail , Wilbur David Pricer
发明人： John Anthony Bracchitta , Michel Salib Michail , Wilbur David Pricer
IPC分类号： H03K3/013 , H03K3/356 , H03K3/037
CPC分类号： H03K3/356113 , H03K3/356165 , H03K3/013
摘要： A soft latch circuit having a first and second inverter is disclosed. The output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The first inverter includes a complimentary pair of field-effect transistors (FETs). The second inverter includes either a complimentary pair of current mirrors, or a current mirror and a complimentary FET, the latter providing improved noise immunity characteristics when the soft latch is set in only one direction.
摘要翻译：公开了具有第一和第二逆变器的软锁存电路。第一反相器的输出端连接到第二反相器的输入，第二反相器的输出连接到第一反相器的输入。第一个反相器包括一对互补的场效应晶体管（FET）。第二个反相器包括互补的电流镜对，或电流镜和互补FET，后者在软锁存器仅设置在一个方向上时提供改善的抗噪声特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式