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1. 发明申请

US20170338821A1 CMOS OUTPUT CIRCUIT 审中-公开
公开(公告)号：US20170338821A1
公开(公告)日：2017-11-23
申请号：US15599815
申请日：2017-05-19
申请人： Rohm Co., Ltd.
发明人： Satoshi Tanaka
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/00 , H03K19/0948
CPC分类号： H03K19/00361 , H03K19/0013 , H03K19/0027 , H03K19/018521 , H03K19/018571 , H03K19/0948
摘要： A CMOS output circuit includes a first P-MOSFET having a source connected to a power supply terminal, a drain connected to an output terminal, and a back gate connected to a first potential terminal; a first N-MOSEFET having a drain connected to the output terminal, a source connected to the ground terminal, and a back gate connected to a second potential terminal; a first potential switching portion arranged to switch whether to connect the first potential terminal to the power supply terminal or to the output terminal; a second potential switching portion arranged to switch whether to connect the second potential terminal to the ground terminal or to the output terminal; a first gate switching portion arranged to switch whether or not to short-circuit the gate of the first P-MOSFET to the first potential terminal; a second gate switching portion arranged to switch whether or not to short-circuit the gate of the first N-MOSFET to the second potential terminal; a first driver arranged to drive the gate of the first P-MOSFET in accordance with a first input signal; a second driver arranged to drive the gate of the first N-MOSFET in accordance with a second input signal; and a control portion arranged to control individual portions of the circuit when turning off both the first P-MOSFET and the first N-MOSFET, so as to connect the first potential terminal to one of the power supply terminal and the output terminal, which has a higher potential, to connect the second potential terminal to one of the ground terminal and the output terminal, which has a lower potential, to short-circuit the gate of the first P-MOSFET to the first potential terminal, and to short-circuit the gate of the first N-MOSFET to the second potential terminal.

2. 发明申请

US20160320789A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING BULK BIAS CONTROL FUNCTION AND METHOD OF DRIVING THE SAME 有权
公开(公告)号：US20160320789A1
公开(公告)日：2016-11-03
申请号：US15206658
申请日：2016-07-11
申请人： SK hynix Inc.
发明人： Yeon Uk KIM
IPC分类号： G05F3/02 , H03K19/00
CPC分类号： G05F3/02 , H03K19/0013 , H03K19/0027 , H03K19/00361
摘要： A semiconductor integrated circuit device having a bulk bias control function is provided. The semiconductor integrated circuit device may be configured to output the first external voltage as a bulk voltage of a transistor in a power-up period, and to output a second external voltage having a higher level than the first external voltage as the bulk voltage of the transistor in a power-down mode.

3. 发明授权

US09473139B2 Threshold logic element with stabilizing feedback 有权
标题翻译：具有稳定反馈的阈值逻辑元件
公开(公告)号：US09473139B2
公开(公告)日：2016-10-18
申请号：US14792183
申请日：2015-07-06
申请人： Sarma Vrudhula , Niranjan Kulkarni
发明人： Sarma Vrudhula , Niranjan Kulkarni
IPC分类号： H03K19/094 , G11C7/00 , H03K19/003 , G11C7/06 , G11C11/16 , G11C13/00 , H03K19/00 , H03K19/017 , H03K19/096 , H03K19/21
CPC分类号： H03K19/00361 , G11C7/065 , G11C11/1673 , G11C13/004 , H03K19/0027 , H03K19/01707 , H03K19/0963 , H03K19/215
摘要： Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise.
摘要翻译：公开了阈值逻辑元件及其操作方法。在一个实施例中，阈值逻辑元件包括被配置为接收第一组逻辑信号的第一输入门网络，被配置为接收第二组逻辑信号的第二输入门网络。差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分逻辑输出。为了使阈值逻辑元件更稳健，差分读出放大器被配置为将差分逻辑输出反馈到第一输入门网络和第二输入门网络。通过提供差分逻辑输出作为反馈，避免了浮动节点问题，并且阈值逻辑元件更能抵抗噪声。

4. 发明申请

US20160173085A1 I/O DRIVING CIRCUIT AND CONTROL SIGNAL GENERATING CIRCUIT 有权
标题翻译： I / O驱动电路和控制信号发生电路
公开(公告)号：US20160173085A1
公开(公告)日：2016-06-16
申请号：US14746856
申请日：2015-06-23
申请人： Mediatek Inc.
发明人： Chen-Feng Chiang , An-Siou Li
IPC分类号： H03K17/687 , H03K17/693
CPC分类号： H03K17/6871 , H03K17/08142 , H03K17/693 , H03K19/0027 , H03K19/00384 , H03K19/018521
摘要： An I/O driving circuit comprising a post driver. The post driver comprises: a first switch device, comprising a first terminal coupled to an I/O voltage, and comprising a second terminal, wherein the first switch device provides an initial driving voltage at the second terminal of the first switch device; and a first voltage providing device, comprising a first terminal coupled to the second terminal of the first switch device, and comprising a second terminal. The first voltage providing device is configured to provide a driving voltage at the second terminal of the first voltage providing device via providing a voltage drop to the initial driving voltage.
摘要翻译：一种包括后置驱动器的I / O驱动电路。所述后驱动器包括：第一开关装置，包括耦合到I / O电压的第一端子，并且包括第二端子，其中所述第一开关装置在所述第一开关装置的所述第二端子处提供初始驱动电压; 以及第一电压提供装置，包括耦合到第一开关装置的第二端子的第一端子，并且包括第二端子。第一电压提供装置被配置为通过向初始驱动电压提供电压降来在第一电压提供装置的第二端提供驱动电压。

5. 发明授权

US09264045B2 Buffer circuit with reduced static leakage through controlled body biasing in FDSOI technology 有权
标题翻译：缓冲电路通过FDSOI技术的受控体偏置降低静电泄漏
公开(公告)号：US09264045B2
公开(公告)日：2016-02-16
申请号：US14231939
申请日：2014-04-01
申请人： STMicroelectronics International N.V.
发明人： Sameer Vashishtha , Saiyid Mohammad Irshad Rizvi
IPC分类号： H03K5/08 , H03K19/0948 , H03K19/003 , H03K19/0185 , H03K19/00
CPC分类号： H03K19/09487 , H03K19/0027 , H03K19/00361 , H03K19/018521
摘要： A buffer includes an input configured to receive a first digital signal having first and second logic states referenced, respectively, to a first high voltage and a first low voltage of a first supply domain. A first inverter circuit includes a pMOS transistor and nMOS transistor having gate terminals connected to the input. A second inverter is connected in series with the output of the first inverter. The second inverter has an output configured to generate a second digital signal having first and second logic states referenced, respectively, to a second high voltage and a second low voltage of a second, different, supply domain, wherein at least the second high voltage is greater than the first high voltage. A feedback circuit is configured to apply the second digital signal as a bias to a transistor body of the p-MOS transistor of the first inverter circuit.
摘要翻译：缓冲器包括被配置为接收具有分别被引用到第一供电域的第一高电压和第一低电压的第一和第二逻辑状态的第一数字信号的输入。第一反相器电路包括具有连接到输入的栅极端子的pMOS晶体管和nMOS晶体管。第二反相器与第一反相器的输出串联。第二反相器具有被配置为产生具有第一和第二逻辑状态的第二数字信号的第二数字信号，第一和第二逻辑状态分别被称为第二高电压和第二不同供电域的第二低电压，其中至少第二高电压是大于第一高电压。反馈电路被配置为将第二数字信号作为偏置施加到第一反相器电路的p-MOS晶体管的晶体管本体。

6. 发明申请

US20160036419A1 METHOD AND APPARATUS FOR CALIBRATING CMOS INVERTER 有权
标题翻译：用于校准CMOS逆变器的方法和装置
公开(公告)号：US20160036419A1
公开(公告)日：2016-02-04
申请号：US14450335
申请日：2014-08-04
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang (Leon) Lin
IPC分类号： H03K3/037 , H03K3/356
CPC分类号： H03K3/0375 , H03K3/037 , H03K3/356104 , H03K19/0027
摘要： A circuit and method for calibrating CMOS (complementary metal-oxide semiconductor) inverters are provided. In a circuit, a first tunable CMOS inverter, controlled by a control signal, receives a first voltage from a first circuit node and outputs a second voltage to a second circuit node. A second tunable CMOS inverter, controlled by the control signal, receives the second voltage from the second circuit node and outputs the first voltage to the first circuit node. A resistor couples the first circuit node to the second circuit node. A switch, controlled by a reset signal, conditionally shorts the first circuit node to the second circuit node. A finite state machine receives the first voltage and the second voltage and outputs the reset signal and the control signal, wherein the control signal is adjusted based on a difference between the first voltage and the second voltage.
摘要翻译：提供了用于校准CMOS（互补金属氧化物半导体）逆变器的电路和方法。在电路中，由控制信号控制的第一可调CMOS反相器从第一电路节点接收第一电压，并向第二电路节点输出第二电压。由控制信号控制的第二可调CMOS反相器从第二电路节点接收第二电压，并将第一电压输出到第一电路节点。电阻器将第一电路节点耦合到第二电路节点。由复位信号控制的开关有条件地将第一电路节点短路到第二电路节点。有限状态机接收第一电压和第二电压并输出复位信号和控制信号，其中基于第一电压和第二电压之间的差来调整控制信号。

7. 发明申请

US20150092499A1 SLEW RATE MODULATION 有权
标题翻译：睡眠率调整
公开(公告)号：US20150092499A1
公开(公告)日：2015-04-02
申请号：US14567903
申请日：2014-12-11
申请人： Micron Technology, Inc.
发明人： Daesik Song
IPC分类号： G11C16/24 , G11C7/12
CPC分类号： G11C16/24 , G11C7/12 , H03K19/0027 , H03K19/018528 , H03K19/018585
摘要： Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.
摘要翻译：装置和方法可以操作，使得控制晶体管栅极处的数据信号的到达时间以在不同时间切换晶体管，以调制节点上的信号的转换速率。还描述了另外的实施例。

8. 发明授权

US08994401B2 Semiconductor device with buffer and replica circuits 有权
标题翻译：具有缓冲器和复制电路的半导体器件
公开(公告)号：US08994401B2
公开(公告)日：2015-03-31
申请号：US14018784
申请日：2013-09-05
申请人： Elpida Memory, Inc.
发明人： Toru Hatakeyama , Toru Ishikawa
IPC分类号： H03K19/0175 , H03K19/00
CPC分类号： H03K19/0027 , G11C5/06 , G11C7/1087
摘要： A semiconductor device includes a first input buffer adjusting a logic threshold voltage, a first replica circuit, a first reference voltage generating circuit, and a first comparator circuit. The first replica circuit is identical in circuit configuration to the first input buffer. The first replica circuit has an input and an output connected to the input. The first replica circuit generates the logic threshold voltage as an output voltage. The first reference voltage generating circuit generates a first reference voltage. The first comparator circuit compares the logic threshold voltage as an output voltage of the first replica circuit to the first reference voltage to generate a first threshold adjustment signal. The first comparator circuit supplies the first threshold adjustment signal to the first input buffer and the first replica circuit. The first threshold adjustment signal allows the first input buffer to adjust the logic threshold voltage.
摘要翻译：半导体器件包括调整逻辑阈值电压的第一输入缓冲器，第一复制电路，第一参考电压产生电路和第一比较器电路。第一复制电路在电路配置与第一输入缓冲器相同。第一个复制电路具有连接到输入的输入和输出。第一个复制电路产生逻辑阈值电压作为输出电压。第一参考电压产生电路产生第一参考电压。第一比较器电路将逻辑阈值电压作为第一复制电路的输出电压与第一参考电压进行比较，以产生第一阈值调整信号。第一比较器电路将第一阈值调整信号提供给第一输入缓冲器和第一复制电路。第一阈值调整信号允许第一输入缓冲器调整逻辑阈值电压。

9. 发明授权

US08922251B2 Buffer control circuit and integrated circuit including the same 有权
标题翻译：缓冲器控制电路和集成电路包括相同
公开(公告)号：US08922251B2
公开(公告)日：2014-12-30
申请号：US13333983
申请日：2011-12-21
申请人： Taek-Sang Song , Dae-Han Kwon
发明人： Taek-Sang Song , Dae-Han Kwon
IPC分类号： H03B1/00 , H03K3/00 , H03K5/24 , H03K19/00 , H03K19/0948
CPC分类号： H03K5/2481 , H03K19/0027 , H03K19/0948
摘要： A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.
摘要翻译：缓冲器控制电路包括：电流供给单元，被配置为响应于代码提供电流并调节电流;放大缓冲器，被配置为使用电流进行操作并输出通过比较参考电位和参考电位获得的值;配置的第二缓冲器以缓冲第一缓冲器的输出;以及代码生成单元，被配置为响应于第二缓冲器的输出而生成代码。

10. 发明授权

US08697512B2 Systems and methods for integrated circuits comprising multiple body biasing domains 有权
标题翻译：包括多个主体偏置域的集成电路的系统和方法
公开(公告)号：US08697512B2
公开(公告)日：2014-04-15
申请号：US12968032
申请日：2010-12-14
申请人： Kleanthes G. Koniaris , Robert Paul Masleid , James B. Burr
发明人： Kleanthes G. Koniaris , Robert Paul Masleid , James B. Burr
IPC分类号： H01L29/72
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译：包括多个主体偏置域的集成电路的系统和方法。根据第一实施例，半导体结构包括第一类型材料的衬底。包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。

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