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1. 发明授权

US06453431B1 System technique for detecting soft errors in statically coupled CMOS logic 失效
标题翻译：用于检测静态耦合CMOS逻辑中的软错误的系统技术
公开(公告)号：US06453431B1
公开(公告)日：2002-09-17
申请号：US09346509
申请日：1999-07-01
申请人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
发明人： Kerry Bernstein , Andres Bryant , William A. Klaasen , Wilbur David Pricer
IPC分类号： G06K504
CPC分类号： G11C5/005 , G06F11/00
摘要： Circuit for detecting error transients in logic circuits due to atomic events or other non-recurring noise sources includes a first circuit coupled to a data line for sensing a first signal on the data line at a first point in time (T1) and a second circuit coupled to the data line for sensing the first signal on the data line at a second point in time (T2) such that a time difference between T1 and T2 is small enough so that the first signal is still present on the data line in the absence of a perturbation event and such that the time difference between T1 and T2 is large enough so that any such perturbation event is resolved. A compare circuit coupled to the first and second circuits compares the sensing of the first signal by the first and second circuits, and generates an error signal in response to a non-compare.
摘要翻译：用于检测由于原子事件或其他非循环噪声源引起的逻辑电路中的错误瞬变的电路包括耦合到数据线的第一电路，用于感测在第一时间点（T1）的数据线上的第一信号，以及第二电路耦合到数据线，用于在第二时间点（T2）感测数据线上的第一信号，使得T1和T2之间的时间差足够小，使得第一信号在不存在的情况下仍然存在于数据线上的扰动事件，并且使得T1和T2之间的时间差足够大，使得任何这样的扰动事件被解决。耦合到第一和第二电路的比较电路比较第一和第二电路对第一信号的感测，并且响应于非比较而产生误差信号。

2. 发明授权

US06545330B1 On chip alpha-particle detector 有权
公开(公告)号：US06545330B1
公开(公告)日：2003-04-08
申请号：US09614234
申请日：2000-07-12
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2714
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

3. 发明授权

US06645789B2 On chip alpha-particle detector 失效
公开(公告)号：US06645789B2
公开(公告)日：2003-11-11
申请号：US10246136
申请日：2002-09-18
申请人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
发明人： Kerry Bernstein , Andres Bryant , Wayne J. Howell , William A. Klaasen , Wilbur D. Pricer , Anthony K. Stamper
IPC分类号： H01L2100
CPC分类号： H01L27/14683 , G01T1/244 , H01L27/14659 , H01L31/115 , H01L31/118
摘要： An IC chip comprising, a nearby or remote source capable of particle emissions; circuitry formed in the IC chip that is adversely affected by impacts of particle emissions from said source; and a particle detector formed in the IC chip between the circuitry and source for detecting said particle emissions. In one embodiment of the present invention, the source comprises a solder ball that is formed on a surface of the IC chip, and the solder ball is capable of emitting alpha-particles. The particle emissions detector of the present invention is a reverse biased Schottky diode. The IC chip is formed by (a) providing an IC chip having at least one layer of particle sensitive circuitry formed therein; (b) forming another layer having at least one particle sensor region situated therein on a surface of said IC chip; and (c) optionally, forming at least one particle emission source over said another layer.

4. 发明申请

US20090295432A1 CMOS BACK-GATED KEEPER TECHNIQUE 失效
公开(公告)号：US20090295432A1
公开(公告)日：2009-12-03
申请号：US12538652
申请日：2009-08-10
申请人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
发明人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
IPC分类号： H03K19/20
CPC分类号： H03K19/0008 , H03K3/356104 , H03K2217/0018
摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
摘要翻译：详细描述了利用并接触MOSFET器件的第四端子（衬底/本体）的逻辑电路和栅极的构造和操作的新颖方法。新颖的结构和操作提供了当主动接通（以增加过驱动和性能）时以及在关闭时较高的相对阈值电压（以减少泄漏功率）时将这种体接触的MOSFET器件保持在较低的阈值电压（VTh）。因为门的门限电位与其电位相反地移动，所以一般来说，给定器件的器件必须与器件的漏极电压相反，以达到改善器件所需的阈值电位调制效应，电路，门和逻辑家庭操作。

5. 发明授权

US06404236B1 Domino logic circuit having multiplicity of gate dielectric thicknesses 有权
标题翻译：具有多个栅介质厚度的多米诺逻辑电路
公开(公告)号：US06404236B1
公开(公告)日：2002-06-11
申请号：US09811967
申请日：2001-03-19
申请人： Kerry Bernstein , Andres Bryant , Robert J. Gauthier, Jr. , Edward Joseph Nowak , Minh Ho Tong
发明人： Kerry Bernstein , Andres Bryant , Robert J. Gauthier, Jr. , Edward Joseph Nowak , Minh Ho Tong
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.
摘要翻译：公开了具有时钟预充电的多米诺骨牌逻辑电路。多米诺骨牌逻辑电路包括预充电晶体管，隔离晶体管和多个评估晶体管。连接到电源，预充电晶体管接收时钟输入。隔离晶体管连接到地，并接收时钟输入。耦合在预充电晶体管和隔离晶体管之间的每个输入晶体管接收信号输入。评估晶体管的栅介质厚度小于预充电晶体管的栅介质厚度。

6. 发明授权

US07750682B2 CMOS back-gated keeper technique 失效
公开(公告)号：US07750682B2
公开(公告)日：2010-07-06
申请号：US12045500
申请日：2008-03-10
申请人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
发明人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
IPC分类号： H03K19/094
CPC分类号： H03K19/0008 , H03K3/356104 , H03K2217/0018
摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

7. 发明授权

US07750677B2 CMOS back-gated keeper technique 失效
标题翻译： CMOS后门控技术
公开(公告)号：US07750677B2
公开(公告)日：2010-07-06
申请号：US12538652
申请日：2009-08-10
申请人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
发明人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
IPC分类号： H03K19/21
CPC分类号： H03K19/0008 , H03K3/356104 , H03K2217/0018
摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.
摘要翻译：详细描述了利用并接触MOSFET器件的第四端子（衬底/本体）的逻辑电路和栅极的构造和操作的新颖方法。新颖的结构和操作提供了当主动接通（以增加过驱动和性能）时以及在关闭时较高的相对阈值电压（以减少泄漏功率）时将这种体接触的MOSFET器件保持在较低的阈值电压（VTh）。因为门的门限电位与其电位相反地移动，所以一般来说，给定器件的器件必须与器件的漏极电压相反，以达到改善器件所需的阈值电位调制效应，电路，门和逻辑家庭操作。

8. 发明申请

US20090224803A1 CMOS BACK-GATED KEEPER TECHNIQUE 失效
公开(公告)号：US20090224803A1
公开(公告)日：2009-09-10
申请号：US12045500
申请日：2008-03-10
申请人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
发明人： Kerry Bernstein , Andres Bryant , Wilfried Haensch
IPC分类号： H03K19/20
CPC分类号： H03K19/0008 , H03K3/356104 , H03K2217/0018
摘要： A novel methodology for the construction and operation of logical circuits and gates that make use of and contact to a fourth terminal (substrates/bodies) of MOSFET devices is described in detail. The novel construction and operation provides for maintaining such body-contacted MOSFET devices at a lower threshold voltage (VTh) when actively on (to increase overdrive and performance), and at a higher relative threshold voltage when off (to reduce leakage power). Because the threshold potential of a gate moves inversely to its body potential, it follows then that in general, the body of a given device must be tied to the inverse of the device's drain voltage to achieve such a desirable threshold potential modulation effect for improved device, circuit, gate and logical family operation.

9. 发明授权

US09768304B2 Method of fabricating a FINFET having a gate structure disposed at least partially at a bend region of the semiconductor fin 有权
公开(公告)号：US09768304B2
公开(公告)日：2017-09-19
申请号：US13492108
申请日：2012-06-08
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L21/20 , H01L29/78 , H01L21/8238 , H01L27/12 , H01L29/10 , H01L21/3115 , H01L21/762 , H01L29/66
CPC分类号： H01L29/785 , H01L21/31155 , H01L21/76283 , H01L21/823807 , H01L21/823821 , H01L21/823878 , H01L27/1203 , H01L29/1037 , H01L29/66621 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/7849
摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

10. 发明授权

US08941180B2 Integrated circuit structure incorporating one or more asymmetric field effect transistors as power gates for an electronic circuit with stacked symmetric field effect transistors 有权
标题翻译：集成电路结构，其包括一个或多个不对称场效应晶体管作为具有堆叠对称场效应晶体管的电子电路的功率门
公开(公告)号：US08941180B2
公开(公告)日：2015-01-27
申请号：US13044872
申请日：2011-03-10
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak
IPC分类号： H01L27/02 , H01L27/12 , H01L21/8234 , H01L29/786 , H01L21/8238
CPC分类号： H01L27/1203 , H01L21/823412 , H01L21/823418 , H01L21/823807 , H01L21/823814 , H01L29/78624
摘要： Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin).
摘要翻译：公开了具有不对称FET作为电子电路的功率门的集成电路，其具有至少两个堆叠的对称场效应晶体管。非对称FET具有不对称的卤素配置（即，具有比漏极侧卤素更高的掺杂剂浓度的单个源极卤素或源极卤素）和非对称源极/漏极延伸配置（即，源极延伸可以通过栅极结构比漏极延伸更大程度地重叠和/或源极延伸可以具有比漏极延伸更高的掺杂剂浓度）。结果，不对称FET具有低截止电流。在操作中，当电子电路处于待机状态时，不对称FET被关闭，并且由于低关断电流（Ioff），有效地减少了来自电子电路的待机漏电流。另外，避免使用电子电路内的层叠的非对称场效应晶体管本身可以防止由于线性漏极电流（Idlin）的降低导致的性能劣化。

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