专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5444012A Method for manufacturing semiconductor integrated circuit device having a fuse element 失效
标题翻译：具有熔丝元件的半导体集成电路器件的制造方法
公开(公告)号：US5444012A
公开(公告)日：1995-08-22
申请号：US278073
申请日：1994-07-20
申请人： Keiichi Yoshizumi , Kazushi Fukuda , Seiichi Ariga , Shuji Ikeda , Makoto Saeki , Kiyoshi Nagai , Soichiro Hashiba , Shinji Nishihara , Fumiyuki Kanai
发明人： Keiichi Yoshizumi , Kazushi Fukuda , Seiichi Ariga , Shuji Ikeda , Makoto Saeki , Kiyoshi Nagai , Soichiro Hashiba , Shinji Nishihara , Fumiyuki Kanai
IPC分类号： H01L21/66 , H01L21/768 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L23/522 , H01L23/525 , H01L27/04 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L23/5256 , H01L2924/0002 , Y10S148/055
摘要： In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.
摘要翻译：在将构成最终钝化膜的一部分的氧化硅膜沉积到形成在层间绝缘膜上的接合焊盘上的情况下，将氧化硅沉积步骤分成两个阶段，在第一次沉积之后，通过蚀刻将接合焊盘一次曝光，然后进行第二沉积，由此形成在层间绝缘膜下面的熔丝元件上形成两级沉积的氧化硅膜，而在焊盘上仅形成沉积在第二层中的氧化硅膜阶段。结果，在蚀刻聚酰亚胺树脂，氮化硅膜和氧化硅膜时，连续地露出接合焊盘，在同时形成的孔的底部和熔丝之间保持足够的绝缘膜厚度元件。此后，在将探针施加到接合焊盘的同时进行电气测试，并且如果需要，则切割位于孔下方的熔丝元件。

2. 发明授权

US5543652A Semiconductor device having a two-channel MISFET arrangement defined by I-V characteristic having a negative resistance curve and SRAM cells employing the same 失效
标题翻译：具有由具有负电阻曲线的I-V特性定义的双通道MISFET布置的半导体器件以及采用该双通道MISFET布置的SRAM单元
公开(公告)号：US5543652A
公开(公告)日：1996-08-06
申请号：US98893
申请日：1993-07-29
申请人： Shuji Ikeda , Makoto Saeki
发明人： Shuji Ikeda , Makoto Saeki
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8244 , H01L27/11 , H01L29/78 , H01L29/786 , H01L29/88 , H01L27/01 , H01L29/76
CPC分类号： H01L29/78696 , H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904
摘要： Negative characteristic MISFETs, which are of the same channel conductivity type and which have different threshold voltages, are formed in a doped silicon thin film deposited over a substrate and are connected in channel-to-channel series with each other. The pair of series-connected negative characteristic MISFETs, a resistive element, an information storage capacitive element and a transfer MISFET constitute an SRAM memory cell. Equivalently, a negative characteristic MISFET having a current-voltage characteristic defined by a negative resistance curve can be used in lieu of the pair of series-connected negative characteristic MISFETs in the formation of the individual memory cells of the SRAM. The negative resistance curve of the negative characteristic MISFET is shaped such that the linear current-voltage characteristic curve corresponding to the resistive element of the memory cell intersects the negative resistance curve at at least three location points. The negative characteristic MISFET, like the pair of series-connected negative characteristic MISFETs, has an active region formed in a doped thin film silicon (polycrystalline silicon) layer insulatedly above a substrate main surface. The resistive element is also formed in a thin film silicon layer either integrally with the negative characteristic MISFET or in a separate thin film silicon layer and in series electrical connection with the negative characteristic MISFET.
摘要翻译：具有相同沟道导电类型且具有不同阈值电压的负特性MISFET形成在沉积在衬底上并以通道间通道串联连接的掺杂硅薄膜中。一对串联负特性MISFET，电阻元件，信息存储电容元件和转移MISFET构成SRAM存储单元。等效地，可以使用由负电阻曲线限定的电流 - 电压特性的负特性MISFET来代替在SRAM的各个存储单元的形成中的一对串联负特性MISFET。负特性MISFET的负电阻曲线被成形为使得对应于存储单元的电阻元件的线性电流 - 电压特性曲线在至少三个位置点处与负电阻曲线相交。负极特性MISFET，像一对串联连接的负特性MISFET一样，具有在衬底主表面上绝缘的掺杂薄膜硅（多晶硅）层中形成的有源区。电阻元件也与负特性MISFET或单独的薄膜硅层整体地形成在薄膜硅层中，并与负特性MISFET串联电连接。

3. 发明授权

US5373471A Semiconductor memory device having redundancy memory cells for replacing defective 失效
标题翻译：具有用于替换有缺陷的冗余存储单元的半导体存储器件
公开(公告)号：US5373471A
公开(公告)日：1994-12-13
申请号：US934332
申请日：1992-08-25
申请人： Makoto Saeki , Kiyoshi Nagai , Hisae Yamamura , Tadashi Abe , Takeshi Fukazawa
发明人： Makoto Saeki , Kiyoshi Nagai , Hisae Yamamura , Tadashi Abe , Takeshi Fukazawa
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/846
摘要： In case an address is to access a defective memory cell, a defective memory cell in a memory cell area contained in one of paired memory mats is selected in parallel with a redundant memory cell in a redundant memory cell area contained in the other memory mat. At this time of selecting the redundant main word line for selecting the redundant memory cell, there is not required the logical operation for deciding whether or not the redundant use of the access address fed from the outside is proper. For example, the redundant main word line is set to the select level on the basis of a chip select signal. As a result, the drive start timing of the redundant main word line is not delayed in the least from the drive start timing of the main word line. Thus, it is possible to prevent the event that the select drive timing of the redundant sub word line is delayed on account of the delay in the drive timing of the redundant main word line.
摘要翻译：在地址要访问有缺陷的存储单元的情况下，在包含在其中一个存储器堆中的存储单元区域中的有缺陷的存储器单元与冗余存储器单元并联地选择在另一存储器堆中所包含的冗余存储单元区域中。在选择用于选择冗余存储单元的冗余主字线时，不需要用于判断从外部馈送的访问地址的冗余使用是否合适的逻辑操作。例如，基于片选信号将冗余主字线设定为选择电平。结果，冗余主字线的驱动开始定时至少不会从主字线的驱动开始定时延迟。因此，可以防止由于冗余主字线的驱动定时的延迟而使冗余子字线的选择驱动定时被延迟的事件。

4. 发明授权

US5629898A Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device 失效
标题翻译：动态存储器件，存储器模块和刷新动态存储器件的方法
公开(公告)号：US5629898A
公开(公告)日：1997-05-13
申请号：US607977
申请日：1996-02-29
申请人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
发明人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4016 , G11C2211/4061
摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.
摘要翻译：对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。从刷新地址计数器输出的进位信号由分频器分频。对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中。根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效。

5. 发明授权

US5726967A Disk playback apparatus for a disk player 失效
标题翻译：磁盘播放机的磁盘播放装置
公开(公告)号：US5726967A
公开(公告)日：1998-03-10
申请号：US654721
申请日：1996-05-29
申请人： Shinsaku Tanaka , Tadao Arata , Akira Iwakiri , Makoto Saeki
发明人： Shinsaku Tanaka , Tadao Arata , Akira Iwakiri , Makoto Saeki
IPC分类号： G11B17/22 , G11B17/26 , G11B17/10 , G11B17/04
CPC分类号： G11B17/223 , G11B17/26
摘要： A disk playback apparatus comprises a stocker including a plurality of shelves for compact disks, a pallet disposed adjacent to the stocker, a lift stage for moving the stocker up and down so that a selected one of the shelves is located in a position higher than the pallet for a predetermined distance, a loader capable of reciprocating between an unloading position on the stocker side and a loading position on the pallet side, and a lifter in the loader. As the loader moves from the unloading position toward the loading position, the lifter lowers and feeds the disk on the selected shelf to the pallet while drawing out the disk from the stocker. As the loader moves from the loading position toward the unloading position, the lifter raises and returns the disk on the pallet to the selected shelf while pushing back the disk toward the stocker.
摘要翻译：一种盘播放装置包括一个储盘器，该贮存器包括用于光盘的多个搁架，与该储盘器相邻设置的托盘，用于上下移动该储盘架的升降台，使得所选择的一个搁板位于高于托盘预定距离，能够在储料器侧的卸载位置和托盘侧的装载位置之间往复运动的装载机和装载机中的升降机。当装载机从卸载位置移动到装载位置时，升降器降低并将所选择的货架上的盘送入托盘，同时从储料器中拉出盘。当装载机从装载位置移动到卸载位置时，提升器将托盘上的盘返回到选定的货架上，同时将盘向储盘器推回。

6. 发明授权

US5345421A High speed, low noise semiconductor storage device 失效
标题翻译：高速，低噪音的半导体存储设备
公开(公告)号：US5345421A
公开(公告)日：1994-09-06
申请号：US905745
申请日：1992-06-29
申请人： Masahiro Iwamura , Tatsumi Yamauchi , Makoto Saeki , Hideaki Uchida
发明人： Masahiro Iwamura , Tatsumi Yamauchi , Makoto Saeki , Hideaki Uchida
IPC分类号： G11C11/417 , G11C11/401 , G11C11/409 , H03K19/003 , H03K19/00
CPC分类号： H03K19/00361
摘要： A wide-bit output semiconductor storage device of high speed and low noise is provided in which output circuits are grouped into two groups and the two output circuit groups are so controlled as to be switched in directions of levels which are opposite to each other.
摘要翻译：提供了一种高速和低噪声的宽位输出半导体存储器件，其中输出电路被分组成两组，并且两个输出电路组被如此控制以在彼此相反的电平的方向上切换。

7. 发明授权

US5768214A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5768214A
公开(公告)日：1998-06-16
申请号：US689548
申请日：1996-08-09
申请人： Ken Saitoh , Shunichi Sukegawa , Tadashi Tachibana , Makoto Saeki , Yukihide Suzuki
发明人： Ken Saitoh , Shunichi Sukegawa , Tadashi Tachibana , Makoto Saeki , Yukihide Suzuki
IPC分类号： G11C11/41 , G11C7/06 , G11C8/18 , G11C11/409 , G11C8/00
CPC分类号： G11C8/18 , G11C7/06
摘要： A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.
摘要翻译：一种半导体存储器件，其中防止了与输入地址信号的不期望的电平变化有关的错误操作，并且确保了主放大器的适当的操作。半导体存储器件具有主放大器激活脉冲发生器112'，其包括响应灵敏度降低电路10，响应灵敏度选择器12和主放大器激活脉冲发生器14.响应灵敏度降低电路10可以降低响应灵敏度降低电路10的响应灵敏度或输入灵敏度电路112'相对于输入地址转换检测脉冲ATD。响应灵敏度选择器12根据主放大器激活脉冲发生器14的输出状态选择第一输入端子A1或第二输入端子A2。因此，当没有主放大器从主振荡器激活脉冲MA的输出放大器激活脉冲发生器14，响应灵敏度选择器12切换到第一输入端子A1以选择响应灵敏度降低电路10; 当输出主放大器激活脉冲MA时，选择器12切换到第二输入端A2以选择旁路电路11。

8. 发明授权

US5761149A Dynamic RAM 失效
标题翻译：动态RAM
公开(公告)号：US5761149A
公开(公告)日：1998-06-02
申请号：US679724
申请日：1996-07-12
申请人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
发明人： Yukihide Suzuki , Kanehide Kenmizaki , Tsugio Takahashi , Masayuki Nakamura , Makoto Saeki , Chisa Makimura , Katsuo Komatsuzaki , Shunichi Sukegawa
IPC分类号： H01L27/108 , G11C8/14 , G11C11/401 , G11C11/407 , G11C11/418 , G11C29/00 , G11C29/04 , H01L21/8242 , H01L27/105 , G11C8/00
CPC分类号： G11C29/80 , G11C11/418 , G11C29/83 , G11C8/14 , H01L27/105
摘要： A dynamic RAM is provided with a main word lines; a plurality of subsidiary word lines which are arranged in the direction of bit lines crossing the main word line and to which a plurality of dynamic memory cells are connected; a plurality of subsidiary word selection lines which are extended so as to perpendicularly intersect the main word line and through which a selection signal for selecting one of the plurality of subsidiary word lines is transmitted; and a logic circuit for receiving a selection signal from the main word line and a selection signal from each of the subsidiary word selection lines to thereby form a selection signal for selecting one of the subsidiary word lines. In the dynamic RAM, the voltage level of each of the main word line and the subsidiary word selection lines is made to be equal to the ground potential when the line is in a not-selected state.
摘要翻译：动态RAM具有主字线; 多个辅助字线，沿着与主字线交叉的位线的方向排列，多个动态存储单元被连接到该多个辅助字线; 多个副字选择线，其被延伸成与主字线垂直相交，并且通过该多个副字选择线发送用于选择多个辅助字线中的一个的选择信号; 以及用于从主字线接收选择信号的逻辑电路和来自每个辅助字选择线的选择信号，从而形成用于选择一个辅助字线的选择信号。在动态RAM中，当线处于未选择状态时，使主字线和副字选择线中的每一个的电压电平等于地电位。

9. 发明授权

US5805522A Address access path control circuit 失效
标题翻译：地址访问路径控制电路
公开(公告)号：US5805522A
公开(公告)日：1998-09-08
申请号：US706373
申请日：1996-08-30
申请人： Shunichi Sukegawa , Koichi Abe , Makoto Saeki , Yukihide Suzuki
发明人： Shunichi Sukegawa , Koichi Abe , Makoto Saeki , Yukihide Suzuki
IPC分类号： G11C11/413 , G11C7/10 , G11C11/401 , G11C11/408 , G11C11/409 , G11C8/00 , G11C7/00
CPC分类号： G11C7/1051 , G11C7/1048
摘要： An address access path control circuit designed for shorter access time and small the layout area with low power consumption and noise. Our control circuit has a latching circuit LMO2A, a main output circuit MO3, and a common-bus driving circuit CBD for holding the level of a pair of common-buses CB/CB.sub.-- at the ground level during a prescribed period of time in which address transition takes place while the read data is output to common-buses CB/CB.sub.-- at a timing corresponding to the address signal. A data output buffer DO-BUF outputs to the outside the data transmitted from common-buses CB/CB.sub.-- to data output lines OD/OD.sub.-- in response to the input of control signal DOE. A control signal DOE is input to data output buffer DO-BUF during the period in which data output lines OD/OD.sub.-- are at the ground level.
摘要翻译：一种地址访问路径控制电路，设计用于更短的访问时间，并且具有低功耗和噪声的布局区域较小。我们的控制电路有一个锁存电路LMO2A，一个主输出电路MO3和一个共用总线驱动电路CBD，用于在一段规定的时间内保持一对公共汽车CB / CB-的电平，在与地址信号相对应的定时将读取数据输出到公共总线CB / CB-时发生地址转换。响应于控制信号DOE的输入，数据输出缓冲器DO-BUF向外部输出从公共总线CB / CB-发送到数据输出线OD / OD-的数据。在数据输出线OD / OD-处于地电平的期间，控制信号DOE输入到数据输出缓冲器DO-BUF。

10. 发明授权

US4876669A MOS static type RAM having a variable load 失效
标题翻译：具有可变负载的MOS静态型RAM
公开(公告)号：US4876669A
公开(公告)日：1989-10-24
申请号：US203459
申请日：1988-06-07
申请人： Sho Yamamoto , Osamu Minato , Makoto Saeki , Yasuo Yoshitomi , Hideaki Nakamura , Masaaki Kubotera
发明人： Sho Yamamoto , Osamu Minato , Makoto Saeki , Yasuo Yoshitomi , Hideaki Nakamura , Masaaki Kubotera
IPC分类号： G11C11/417 , G11C11/34 , G11C11/419
CPC分类号： G11C11/419
摘要： An MOS static type RAM has a memory cell array comprising of a plurality of static type memory cells arranged in matrix, a plurality of data lines connected to the data input-output terminals of the respective memory cells and a plurality of word lines connected to the selection terminals of the respective memory cells. Data line load circuits are disposed between the power terminal of the circuit and the data lines. Each data line load circuit is kept at a relatively high impedance in the data write-in operation, and at a relatively low impedance in the data read-out operation. The use of the data line load circuits comprised of such variable impedance circuits can speed up the operating speed of the RAM and can accomplish lower power consumption.
摘要翻译： MOS静态型RAM具有存储单元阵列，其包括以矩阵形式排列的多个静态型存储单元，连接到各个存储单元的数据输入 - 输出端的多条数据线以及与该存储单元连接的多条字线各个存储单元的选择端。数据线负载电路设置在电路的电源端子和数据线之间。每个数据线路负载电路在数据写入操作中保持相对高的阻抗，并且在数据读出操作中处于相对较低的阻抗。由这种可变阻抗电路构成的数据线负载电路的使用可以加速RAM的工作速度并且可以实现更低的功耗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式