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1. 发明授权

US5444012A Method for manufacturing semiconductor integrated circuit device having a fuse element 失效
标题翻译：具有熔丝元件的半导体集成电路器件的制造方法
公开(公告)号：US5444012A
公开(公告)日：1995-08-22
申请号：US278073
申请日：1994-07-20
申请人： Keiichi Yoshizumi , Kazushi Fukuda , Seiichi Ariga , Shuji Ikeda , Makoto Saeki , Kiyoshi Nagai , Soichiro Hashiba , Shinji Nishihara , Fumiyuki Kanai
发明人： Keiichi Yoshizumi , Kazushi Fukuda , Seiichi Ariga , Shuji Ikeda , Makoto Saeki , Kiyoshi Nagai , Soichiro Hashiba , Shinji Nishihara , Fumiyuki Kanai
IPC分类号： H01L21/66 , H01L21/768 , H01L21/82 , H01L21/822 , H01L21/8244 , H01L23/522 , H01L23/525 , H01L27/04 , H01L21/70 , H01L27/00
CPC分类号： H01L27/11 , H01L23/5256 , H01L2924/0002 , Y10S148/055
摘要： In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.
摘要翻译：在将构成最终钝化膜的一部分的氧化硅膜沉积到形成在层间绝缘膜上的接合焊盘上的情况下，将氧化硅沉积步骤分成两个阶段，在第一次沉积之后，通过蚀刻将接合焊盘一次曝光，然后进行第二沉积，由此形成在层间绝缘膜下面的熔丝元件上形成两级沉积的氧化硅膜，而在焊盘上仅形成沉积在第二层中的氧化硅膜阶段。结果，在蚀刻聚酰亚胺树脂，氮化硅膜和氧化硅膜时，连续地露出接合焊盘，在同时形成的孔的底部和熔丝之间保持足够的绝缘膜厚度元件。此后，在将探针施加到接合焊盘的同时进行电气测试，并且如果需要，则切割位于孔下方的熔丝元件。

2. 发明授权

US5880497A Semiconductor integrated circuit device having capacitance element and process of manufacturing the same 失效
标题翻译：具有电容元件的半导体集成电路器件及其制造方法
公开(公告)号：US5880497A
公开(公告)日：1999-03-09
申请号：US592235
申请日：1996-01-26
申请人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
发明人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
IPC分类号： H01L27/11
CPC分类号： H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
摘要翻译：其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

3. 发明授权

US5508540A Semiconductor integrated circuit device and process of manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5508540A
公开(公告)日：1996-04-16
申请号：US190596
申请日：1994-02-02
申请人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
发明人： Shuji Ikeda , Koichi Imato , Kazuo Yoshizaki , Kohji Yamasaki , Soichiro Hashiba , Keiichi Yoshizumi , Yasuko Yoshida , Kousuke Okuyama , Mitsugu Oshima , Kazushi Tomita , Tsuyoshi Tabata , Kazushi Fukuda , Junichi Takano , Toshiaki Yamanaka , Chiemi Hashimoto , Motoko Kawashima , Fumiyuki Kanai , Takashi Hashimoto
IPC分类号： H01L27/11 , H01L27/108 , H01L29/04 , H01L29/76
CPC分类号： H01L27/1108 , Y10S257/903 , Y10S257/904
摘要： A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.
摘要翻译：其存储单元被构造成包括由字线控制的转移MISFET和具有驱动器MISFET和负载MISFET的触发器电路的SRAM。固定在预定电源线上的大面积平板电极布置在负载MISFET上，使得负载MISFET的偏移区域上的平板电极形成开口。在半导体衬底的主表面上形成的转移MISFET和驱动器MISFET上形成具有可渗透氢而不湿度的氮化硅膜，以及沉积在驱动器MISFET上的多晶硅膜形成的负载MISFET。

4. 发明授权

US5780328A Process for producing semiconductor integrated circuit 失效
标题翻译：半导体集成电路制造工艺
公开(公告)号：US5780328A
公开(公告)日：1998-07-14
申请号：US835197
申请日：1997-04-07
申请人： Kazushi Fukuda , Yasuko Yoshida , Yutaka Hoshino , Naotaka Hashimoto , Kyoichiro Asayama , Yuuki Koide , Keiichi Yoshizumi , Eri Okamoto , Satoru Haga , Shuji Ikeda
发明人： Kazushi Fukuda , Yasuko Yoshida , Yutaka Hoshino , Naotaka Hashimoto , Kyoichiro Asayama , Yuuki Koide , Keiichi Yoshizumi , Eri Okamoto , Satoru Haga , Shuji Ikeda
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8244 , H01L27/11 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823871 , H01L27/1052 , H01L27/11 , H01L27/1104
摘要： When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.
摘要翻译：当在衬底中的p型阱中形成用作穿通阻挡层的互补MISFET和p型半导体区域的源区和漏区（n型半导体区和n +型半导体区）具有p型和n型阱时，抑制了穿通止动件的p型杂质被供给到n型阱的馈电部（n +型半导体区）。

5. 发明授权

US06326216B1 Process for producing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件制造工艺
公开(公告)号：US06326216B1
公开(公告)日：2001-12-04
申请号：US08906102
申请日：1997-08-05
申请人： Hisayuki Kato , Hisahiko Abe , Shinji Nishihara , Masahito Yamazaki , Keiichi Yoshizumi
发明人： Hisayuki Kato , Hisahiko Abe , Shinji Nishihara , Masahito Yamazaki , Keiichi Yoshizumi
IPC分类号： H01L2100
CPC分类号： H01L21/02197 , C23C14/088 , C23C14/3414 , H01L21/02266 , H01L21/31691 , H01L27/10814 , H01L28/55
摘要： In order to improve the dielectric constant, residual dielectric polarization, hysteresis characteristics, etc. of a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM, a target having a density of at least 90% of the theoretical value is used in forming, by sputtering, a high-dielectric or ferroelectric thin film for use in the formation of capacitive insulating films of capacitors of a DRAM or a ferroelectric RAM.
摘要翻译：为了提高用于形成DRAM或铁电RAM的电容器的电容绝缘膜的高电介质或铁电薄膜的介电常数，残留介电极化，滞后特性等，具有密度至少90％的理论值用于通过溅射形成用于形成DRAM或铁电RAM的电容器的电容绝缘膜的高电介质或铁电薄膜。

6. 发明授权

US5610856A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5610856A
公开(公告)日：1997-03-11
申请号：US610185
申请日：1996-03-04
申请人： Keiichi Yoshizumi , Satoru Haga , Shuji Ikeda , Kiichi Makuta , Takeshi Fukazawa
发明人： Keiichi Yoshizumi , Satoru Haga , Shuji Ikeda , Kiichi Makuta , Takeshi Fukazawa
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： H01L27/1112 , Y10S257/904
摘要： An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.
摘要翻译：当使用与衬垫层相同层的Al布线精细地构成用于分流的接地电压线时，由于采用这样的布局，使得电阻增加和电迁移阻抗的降低最小化：在连接到互补数据线的一个（数据线）的衬垫层中的连接孔24,26的布置以及连接到互补数据线的另一个（数据线条）的焊盘层中的连接孔的布置是：沿着互补数据线延伸的方向在SRAM中的每两位存储器单元互相反相。

7. 发明授权

US07797851B2 Shape measurement device probe and shape measurement device 有权
公开(公告)号：US07797851B2
公开(公告)日：2010-09-21
申请号：US11919557
申请日：2007-05-08
申请人： Takanori Funabashi , Keiichi Yoshizumi
发明人： Takanori Funabashi , Keiichi Yoshizumi
IPC分类号： G01B5/016 , G01B7/016
CPC分类号： G01B5/012 , G01B7/012 , G01B11/007
摘要： There are provided a shape measurement device capable of measuring shapes irrespective of an inclined direction of a side surface without using a complex device configuration, and a shape measurement device probe arranged in the shape measurement device. In the shape measurement device probe, a connecting mechanism for connecting an attachment member and a swinging member includes a supporting point member arranged on the swinging member and a mounting platform arranged on the attachment member, and connects the swinging member to the attachment member so as to be inclinable in any direction. The attachment member and the swinging member are configured such that a movable side member arranged on the swinging member and a fixed side member arranged on the attachment member generate magnetic attraction force in a non-contacting state with respect to each other, where the arm of the swinging member is biased so as to be directed in the vertical direction by the magnetic attraction force. According to this configuration, a side surface shape inclined in any direction of XY directions and substantially parallel to the Z-direction can be measured.

8. 发明授权

US07759763B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07759763B2
公开(公告)日：2010-07-20
申请号：US12116193
申请日：2008-05-06
申请人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
发明人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/82
CPC分类号： H01L27/0629 , H01L21/823462 , H01L21/823857 , H01L28/20 , H01L28/40
摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
摘要翻译：尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

9. 发明申请

US20100011601A1 Shape measurement device probe and shape measurement device 有权
标题翻译：形状测量装置探头和形状测量装置
公开(公告)号：US20100011601A1
公开(公告)日：2010-01-21
申请号：US11919557
申请日：2007-05-08
申请人： Takanori Funabashi , Keiichi Yoshizumi
发明人： Takanori Funabashi , Keiichi Yoshizumi
IPC分类号： G01B5/16
CPC分类号： G01B5/012 , G01B7/012 , G01B11/007
摘要： There are provided a shape measurement device capable of measuring shapes irrespective of an inclined direction of a side surface without using a complex device configuration, and a shape measurement device probe arranged in the shape measurement device. In the shape measurement device probe, a connecting mechanism for connecting an attachment member and a swinging member includes a supporting point member arranged on the swinging member and a mounting platform arranged on the attachment member, and connects the swinging member to the attachment member so as to be inclinable in any direction. The attachment member and the swinging member are configured such that a movable side member arranged on the swinging member and a fixed side member arranged on the attachment member generate magnetic attraction force in a non-contacting state with respect to each other, where the arm of the swinging member is biased so as to be directed in the vertical direction by the magnetic attraction force. According to this configuration, a side surface shape inclined in any direction of XY directions and substantially parallel to the Z-direction can be measured.
摘要翻译：提供一种形状测量装置，并且不需要使用复杂的装置结构就能够测量与侧面的倾斜方向无关的形状，以及设置在形状测量装置中的形状测量装置探针。在形状测量装置探针中，用于连接安装构件和摆动构件的连接机构包括布置在摆动构件上的支撑构件和布置在安装构件上的安装平台，并且将摆动构件连接到附接构件，以便可以在任何方向倾斜。安装构件和摆动构件被构造成使得设置在摆动构件上的可动侧构件和布置在附接构件上的固定侧构件相对于彼此以非接触状态产生磁吸引力，其中臂摆动构件通过磁吸引力被偏置成在垂直方向上被引导。根据该结构，能够测定沿XY方向的任意方向和Z方向大致平行的侧面形状。

10. 发明授权

US07592669B2 Semiconductor device with MISFET that includes embedded insulating film arranged between source/drain regions and channel 有权
标题翻译：具有MISFET的半导体器件包括布置在源极/漏极区域和沟道之间的嵌入绝缘膜
公开(公告)号：US07592669B2
公开(公告)日：2009-09-22
申请号：US11776380
申请日：2007-07-11
申请人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
发明人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
IPC分类号： H01L29/78
CPC分类号： H01L29/66659 , H01L21/76229 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/0653 , H01L29/456 , H01L29/7835
摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions spaced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain side, in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
摘要翻译：为了抑制或防止在具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应的目的，n +型半导体区域具有与p +型半导体区域相反的导通类型，用于源极和漏极的高电压击穿电压pMIS设置在高击穿电压pMIS的沟道区域的两端，栅极宽度方向的沟槽型隔离部分之间的边界区域以及与p-型半导体隔开的位置处的半导体衬底具有高的击穿电压pMIS的场弛豫功能的区域，以便不与p型半导体区域（特别是在漏极侧）接触。 n +型半导体区域延伸到比沟槽型隔离部分更深的位置。

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