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1. 发明授权

US5706474A Synchronous memory system with asynchronous internal memory operation 失效
标题翻译：具有异步内部存储器操作的同步存储器系统
公开(公告)号：US5706474A
公开(公告)日：1998-01-06
申请号：US455155
申请日：1995-05-31
申请人： Kan Takeuchi , Masashi Horiguchi , Masakazu Aoki , Takeshi Sakata , Hitoshi Tanaka , Katsumi Matsuno
发明人： Kan Takeuchi , Masashi Horiguchi , Masakazu Aoki , Takeshi Sakata , Hitoshi Tanaka , Katsumi Matsuno
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C11/401 , G11C11/409
CPC分类号： G11C7/1072 , G06F13/1689 , Y02B60/1228
摘要： A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.
摘要翻译：提供了一种能够消除由于输入/输出电路和存储块之间的信号延迟引起的处理速率恶化的存储器系统。设计的复杂性也降低了，特别是当存储器系统的规模和芯片面积增加时。存储器芯片包括多个存储器阵列块，每个存储器阵列块包括地址缓冲器和地址计数器，并且基于本地时钟周期进行操作。控制电路与外部设备的时钟同步，同步数据传输电路包括一个缓冲器，该缓冲器调制在本地时钟周期从存储器阵列块到达的串行数据的传输速率，以便与时钟同步的控制电路。外部时钟信号线不分配给存储器阵列块。

2. 发明授权

US5402376A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5402376A
公开(公告)日：1995-03-28
申请号：US103781
申请日：1993-08-10
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

3. 发明授权

US5528548A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5528548A
公开(公告)日：1996-06-18
申请号：US384962
申请日：1995-02-07
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , G11C7/00
CPC分类号： H03K17/693 , G05F1/465
摘要： A semiconductor memory is provided which includes a voltage converter supplying an internal supply voltage in proportion to the greater one of two reference voltages to a circuit in the semiconductor memory. The voltage converter includes a circuit which is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as a voltage dividing circuit. The memory also includes a word line booster for boosting the internal supply voltage.
摘要翻译：提供一种半导体存储器，其包括电压转换器，其向半导体存储器中的电路提供与两个参考电压中的较大一个成比例的内部电源电压。电压转换器包括电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一电路用于产生对外部供电电压的依赖性大于第一电压的依赖性。电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压电路。该存储器还包括用于升高内部电源电压的字线升压器。

4. 发明授权

US5383080A Semiconductor integrated circuit having voltage limiter circuit 失效
标题翻译：具有限压电路的半导体集成电路
公开(公告)号：US5383080A
公开(公告)日：1995-01-17
申请号：US917995
申请日：1992-07-24
申请人： Jun Etoh , Masakazu Aoki , Masashi Horiguchi , Shigeki Ueda , Hitoshi Tanaka , Kazuhiko Kajigaya , Tsugio Takahashi , Hiroshi Kawamoto
发明人： Jun Etoh , Masakazu Aoki , Masashi Horiguchi , Shigeki Ueda , Hitoshi Tanaka , Kazuhiko Kajigaya , Tsugio Takahashi , Hiroshi Kawamoto
IPC分类号： G11C11/407 , G05F1/46 , G11C5/14 , G11C11/401 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/108 , H03G11/00 , H02H3/00
CPC分类号： G11C5/147 , G05F1/465 , H01L27/0248 , H01L2224/48091
摘要： A voltage limiter circuit is disposed in a semiconductor IC chip in order to reduce an operating voltage of an internal circuit of a scaled-down element. A small capacitance of a Vcc wiring by the disposition constitutes a resonance circuit together with an inductance of the Vcc wiring. Resonance at the resonance circuit causes large variation of a supply current and noise. An additional capacitance is connected between the Vcc wiring and a Vss wiring in order to suppress the variation and noise. The capacitance is formed by a PN junction and is connected in series to a damping resistance.
摘要翻译：为了降低按比例缩小的元件的内部电路的工作电压，在半导体IC芯片中设置限压电路。通过配置的Vcc布线的小电容与Vcc布线的电感一起构成谐振电路。谐振电路的共振引起电源电流和噪声的大幅变化。 Vcc接线和Vss接线之间连接一个额外的电容，以抑制变化和噪音。电容由PN结形成，并串联连接到阻尼电阻。

5. 发明授权

US5179539A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5179539A
公开(公告)日：1993-01-12
申请号：US865677
申请日：1992-04-08
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02
CPC分类号： G11C5/147 , G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

6. 发明授权

US5402375A Voltage converter arrangement for a semiconductor memory 失效
标题翻译：用于半导体存储器的电压转换器装置
公开(公告)号：US5402375A
公开(公告)日：1995-03-28
申请号：US207679
申请日：1994-03-09
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , G11C7/00
CPC分类号： H03K17/693 , G05F1/465
摘要： In a voltage converter provided in a semiconductor memory and supplying an internal supply voltage to a circuit in the semiconductor memory, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. The voltage converter includes MOS transistors and differential amplifiers interconnected with one another, as well as voltage dividing means. The memory also includes a word line booster for boosting the internal supply voltage.
摘要翻译：在设置在半导体存储器中的电压转换器中并向半导体存储器中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。电压转换器包括彼此互连的MOS晶体管和差分放大器，以及分压装置。该存储器还包括用于升高内部电源电压的字线升压器。

7. 发明授权

US5376839A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5376839A
公开(公告)日：1994-12-27
申请号：US104340
申请日：1993-08-09
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02 , H03K3/01 , H03K3/26
CPC分类号： G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , G11C5/147 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

8. 发明授权

US5262993A Semiconductor memory having redundancy circuit with means to switch power from a normal memory block to a spare memory block 失效
标题翻译：具有冗余电路的半导体存储器，具有将功率从正常存储块切换到备用存储块的装置
公开(公告)号：US5262993A
公开(公告)日：1993-11-16
申请号：US789024
申请日：1991-11-06
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

9. 发明授权

US5254880A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5254880A
公开(公告)日：1993-10-19
申请号：US863705
申请日：1992-04-03
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02 , H03K3/01 , H03K5/01
CPC分类号： G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , G11C5/147 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

10. 发明授权

US4958325A Low noise semiconductor memory 失效
标题翻译：低噪声半导体存储器
公开(公告)号：US4958325A
公开(公告)日：1990-09-18
申请号：US238375
申请日：1988-08-31
申请人： Yoshinobu Nakagome , Kiyoo Itoh , Masakazu Aoki , Shin'ichi Ikenaga , Masashi Horiguchi , Hitoshi Tanaka
发明人： Yoshinobu Nakagome , Kiyoo Itoh , Masakazu Aoki , Shin'ichi Ikenaga , Masashi Horiguchi , Hitoshi Tanaka
IPC分类号： G11C7/18 , G11C11/4097
CPC分类号： G11C7/18 , G11C11/4097
摘要： A highly integrated semiconductor memory, particularly, a low noise dynamic memory. As the density of integration of the dynamic memory increases, the distance between data lines decreases and a new type of noise, which has hitherto been thought little of, displays itself. To cope with this problem in the semiconductor memory comprising a plurality of pairs of data lines arranged in substantially parallel relationship with each other, respective pairs having substantially the same electric characteristics, connection means provided in association with the respective data line pairs, a plurality of word lines laid to extend perpendicularly to the data line pairs, at least one memory cell connected to at least one of intersections of the word lines with data lines of the pairs, and a plurality of sense amplifier means respectively connected to the data line pairs to differentially detect signal voltages appearing on each data line pair, the plural data line pairs have an alternate arrangement of a pair of data lines transposed at an even number of places and a pair of data lines transposed at an odd number of places, and the sense amplifier means is operative to change voltage on one of the data lines of a pair to a high-level voltage and voltage on the other of the data lines of the pair of a low-level voltage.
摘要翻译：高度集成的半导体存储器，特别是低噪声动态存储器。随着动态存储器的集成密度增加，数据线之间的距离减小，而迄今为止被认为很少的新型噪声显示出来。为了在包括彼此基本上平行关系的多对数据线的半导体存储器中应对这个问题，具有基本上相同电特性的各对具有与各个数据线对相关联地设置的连接装置，与数据线对垂直延伸的字线，至少一个存储单元连接到字线与该对的数据线的交点中的至少一个，以及分别连接到数据线对的多个读出放大器装置差分检测每个数据线对上出现的信号电压，多个数据线对具有在偶数个位置处置换的一对数据线和在奇数个位置处置换的一对数据线的交替排列，并且感测放大器装置可操作以将一对数据线之一上的电压改变为ot上的高电平电压和电压她的数据线是一对低电平的电压。

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