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1. 发明授权

US4994688A Semiconductor device having a reference voltage generating circuit 失效
标题翻译：具有基准电压发生电路的半导体装置
公开(公告)号：US4994688A
公开(公告)日：1991-02-19
申请号：US323966
申请日：1989-03-15
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02
CPC分类号： G11C5/147 , G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , H01L27/0203 , Y10S323/907
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

2. 发明授权

US5179539A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5179539A
公开(公告)日：1993-01-12
申请号：US865677
申请日：1992-04-08
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02
CPC分类号： G11C5/147 , G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

3. 发明授权

US5376839A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5376839A
公开(公告)日：1994-12-27
申请号：US104340
申请日：1993-08-09
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin'ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02 , H03K3/01 , H03K3/26
CPC分类号： G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , G11C5/147 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

4. 发明授权

US5254880A Large scale integrated circuit having low internal operating voltage 失效
标题翻译：具有低内部工作电压的大规模集成电路
公开(公告)号：US5254880A
公开(公告)日：1993-10-19
申请号：US863705
申请日：1992-04-03
申请人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin ichi Ikenaga
发明人： Masashi Horiguchi , Masakazu Aoki , Kiyoo Itoh , Yoshinobu Nakagome , Norio Miyake , Takaaki Noda , Jun Etoh , Hitoshi Tanaka , Shin ichi Ikenaga
IPC分类号： G05F1/46 , G05F3/24 , G11C5/14 , G11C11/4074 , H01L27/02 , H03K3/01 , H03K5/01
CPC分类号： G05F1/465 , G05F3/245 , G05F3/247 , G11C11/4074 , G11C5/147 , H01L27/0203
摘要： Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.
摘要翻译：涉及超大规模半导体集成（ULSI）电路的实际结构，特别是16M位以上的动态随机存取存储器。 ULSI电路使用内部工作电压，并且如何构造参考电压发生电路，并且ULSI电路中的限压器电路是重要的。可以使参考电压发生电路和限压器电路的动作稳定，提高这些电路的特性，能够提高应用于存储单元阵列，外围电路等的这些电路的布局。提供了改进的测试这些电路的方法。

5. 发明授权

US4958325A Low noise semiconductor memory 失效
标题翻译：低噪声半导体存储器
公开(公告)号：US4958325A
公开(公告)日：1990-09-18
申请号：US238375
申请日：1988-08-31
申请人： Yoshinobu Nakagome , Kiyoo Itoh , Masakazu Aoki , Shin'ichi Ikenaga , Masashi Horiguchi , Hitoshi Tanaka
发明人： Yoshinobu Nakagome , Kiyoo Itoh , Masakazu Aoki , Shin'ichi Ikenaga , Masashi Horiguchi , Hitoshi Tanaka
IPC分类号： G11C7/18 , G11C11/4097
CPC分类号： G11C7/18 , G11C11/4097
摘要： A highly integrated semiconductor memory, particularly, a low noise dynamic memory. As the density of integration of the dynamic memory increases, the distance between data lines decreases and a new type of noise, which has hitherto been thought little of, displays itself. To cope with this problem in the semiconductor memory comprising a plurality of pairs of data lines arranged in substantially parallel relationship with each other, respective pairs having substantially the same electric characteristics, connection means provided in association with the respective data line pairs, a plurality of word lines laid to extend perpendicularly to the data line pairs, at least one memory cell connected to at least one of intersections of the word lines with data lines of the pairs, and a plurality of sense amplifier means respectively connected to the data line pairs to differentially detect signal voltages appearing on each data line pair, the plural data line pairs have an alternate arrangement of a pair of data lines transposed at an even number of places and a pair of data lines transposed at an odd number of places, and the sense amplifier means is operative to change voltage on one of the data lines of a pair to a high-level voltage and voltage on the other of the data lines of the pair of a low-level voltage.
摘要翻译：高度集成的半导体存储器，特别是低噪声动态存储器。随着动态存储器的集成密度增加，数据线之间的距离减小，而迄今为止被认为很少的新型噪声显示出来。为了在包括彼此基本上平行关系的多对数据线的半导体存储器中应对这个问题，具有基本上相同电特性的各对具有与各个数据线对相关联地设置的连接装置，与数据线对垂直延伸的字线，至少一个存储单元连接到字线与该对的数据线的交点中的至少一个，以及分别连接到数据线对的多个读出放大器装置差分检测每个数据线对上出现的信号电压，多个数据线对具有在偶数个位置处置换的一对数据线和在奇数个位置处置换的一对数据线的交替排列，并且感测放大器装置可操作以将一对数据线之一上的电压改变为ot上的高电平电压和电压她的数据线是一对低电平的电压。

6. 发明授权

US5677880A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5677880A
公开(公告)日：1997-10-14
申请号：US407850
申请日：1995-03-21
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

7. 发明授权

US5402376A Semiconductor memory having redundancy circuit 失效
标题翻译：具有冗余电路的半导体存储器
公开(公告)号：US5402376A
公开(公告)日：1995-03-28
申请号：US103781
申请日：1993-08-10
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

8. 发明授权

US5262993A Semiconductor memory having redundancy circuit with means to switch power from a normal memory block to a spare memory block 失效
标题翻译：具有冗余电路的半导体存储器，具有将功率从正常存储块切换到备用存储块的装置
公开(公告)号：US5262993A
公开(公告)日：1993-11-16
申请号：US789024
申请日：1991-11-06
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Yoshinobu Nakagome , Hitoshi Tanaka , Kiyoo Itoh
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00
CPC分类号： G11C29/83 , G11C29/832 , G11C5/14
摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.
摘要翻译：在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。

9. 发明授权

US5426616A Semiconductor IC device having a voltage conversion circuit which generates an internal supply voltage having value compensated for external supply voltage variations 失效
标题翻译：具有电压转换电路的半导体IC器件，其产生补偿了外部电源电压变化的值的内部电源电压
公开(公告)号：US5426616A
公开(公告)日：1995-06-20
申请号：US243100
申请日：1994-05-16
申请人： Kazuhiko Kajigaya , Tetsu Udagawa , Kyoko Ishii , Manabu Tsunozaki , Kazuyoshi Oshima , Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Shin'ichi Ikenaga , Kiyoo Itoh
发明人： Kazuhiko Kajigaya , Tetsu Udagawa , Kyoko Ishii , Manabu Tsunozaki , Kazuyoshi Oshima , Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Shin'ichi Ikenaga , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C11/4074 , G11C29/50 , G11C11/407
CPC分类号： G11C29/028 , G11C11/4074 , G11C29/50 , G11C5/147 , G11C11/401 , G11C2029/5004 , Y10T307/344 , Y10T307/615 , Y10T307/62 , Y10T307/696
摘要： A voltage conversion circuit of the present invention is equipped with means for generating a first voltage stabilized with respect to ground potential of a semiconductor integrated circuit device including the circuit, means for generating second voltage stabilized with respect to an external supply voltage of the semiconductor integrated circuit device, and selection means for selecting either the first voltage or the second voltage. The first voltage age, stabilized with respect to the ground potential, is selected and used as the voltage at the time of normal operation, and the second voltage, stabilized with respect to the external supply voltage, is selected and used at the time of aging test. In this case, means for trimming the first voltage and/or the second voltage is, preferably, provided to raise the voltage accuracy.
摘要翻译：本发明的电压转换电路配备有用于产生相对于包括该电路的半导体集成电路器件的接地电位稳定的第一电压的装置，用于产生相对于半导体集成的外部电源电压稳定的第二电压的装置电路装置和用于选择第一电压或第二电压的选择装置。选择相对于地电位稳定的第一电压时间，并将其用作正常操作时的电压，并且在老化时选择并使用相对于外部电源电压稳定的第二电压测试。在这种情况下，优选地提供用于修整第一电压和/或第二电压的装置以提高电压精度。

10. 发明授权

US5272393A Voltage converter of semiconductor device 失效
标题翻译：半导体器件的电压转换器
公开(公告)号：US5272393A
公开(公告)日：1993-12-21
申请号：US790065
申请日：1991-11-12
申请人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
发明人： Masashi Horiguchi , Ryoichi Hori , Kiyoo Itoh , Yoshinobu Nakagome , Masakazu Aoki , Hitoshi Tanaka
IPC分类号： G05F1/46 , H03K17/693 , H03K3/01 , H03K5/22
CPC分类号： H03K17/693 , G05F1/465
摘要： In a voltage converter provided in a semiconductor device and supplying an internal supply voltage to a circuit in the semiconductor device, a circuit is provided for generating a first voltage whose dependency on an external supply voltage is regulated to a predetermined small value, while another circuit is provided for generating a second voltage whose dependency on the external supplying voltage is larger than the dependency of the first voltage. Another circuit selects the first voltage when the semiconductor device is in a state of a standard operation and selects the second voltage when the device is in another state of operation, such as testing or aging. The selected voltage may be converted by a differential amplifier which is constituted by a load of P-channel MOS transistors and a source-coupled pair of N-channel MOS transistors. An output of the differential amplifier is fed back through a directly coupled voltage lowering circuit which generates the converted output.
摘要翻译：在设置在半导体器件中的电压转换器中并向半导体器件中的电路提供内部电源电压的电路，用于产生对外部电源电压的依赖性被调节到预定的小值的第一电压，而另一个电路被提供用于产生对外部供电电压的依赖性大于第一电压的依赖性的第二电压。当半导体器件处于标准操作状态时，另一个电路选择第一电压，并且当器件处于另一种操作状态（例如测试或老化）时选择第二电压。所选择的电压可以由由P沟道MOS晶体管的负载和源极耦合的N沟道MOS晶体管对构成的差分放大器来转换。差分放大器的输出通过直接耦合的降压电路反馈，该电路产生转换的输出。

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