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1. 发明授权

US07611589B2 Methods of spin-on wafer cleaning 有权
标题翻译：旋转晶圆清洗方法
公开(公告)号：US07611589B2
公开(公告)日：2009-11-03
申请号：US11072114
申请日：2005-03-04
申请人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
发明人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
IPC分类号： B08B3/02 , B08B1/04
CPC分类号： B08B1/04 , B08B3/02 , H01L21/67051
摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.
摘要翻译：旋转晶片清洗的方法。该方法包括控制旋转速度和垂直喷水压力。垂直喷射压力和旋转速度基本保持成反比例。晶圆转速在50至1200rpm之间。垂直晶片喷射压力为0.05至100KPa。

2. 发明申请

US20060196526A1 Methods of spin-on wafer cleaning 有权
公开(公告)号：US20060196526A1
公开(公告)日：2006-09-07
申请号：US11072114
申请日：2005-03-04
申请人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
发明人： Jun Wu , Dong-Xuan Lu , Shih-Chi Lin , Wen-Long Lee , Yi-An Jian , Guang-Cheng Wang , Shiu-Ko JangJian , Chyi-Tsong Ni , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23G1/00 , B08B7/00 , B08B3/00
CPC分类号： B08B1/04 , B08B3/02 , H01L21/67051
摘要： A method for spin-on wafer cleaning. The method comprises controlling spin speed and vertical water jet pressure. The vertical jet pressure and the spin speed are substantially maintained in inverse proportion. Wafer spin speed is between 50 to 1200 rpm. Vertical wafer jet pressure is between 0.05 to 100 KPa.

3. 发明授权

US06585826B2 Semiconductor wafer cleaning method to remove residual contamination including metal nitride particles 有权
标题翻译：半导体晶片清洗方法去除残留污染物，包括金属氮化物颗粒
公开(公告)号：US06585826B2
公开(公告)日：2003-07-01
申请号：US10000891
申请日：2001-11-02
申请人： Yali Tai , Shih-Chi Lin , Wen-Long Lee , Francis Wang , Szu-An Wu , Hsi-Kuei Cheng , Ying-Lang Wang
发明人： Yali Tai , Shih-Chi Lin , Wen-Long Lee , Francis Wang , Szu-An Wu , Hsi-Kuei Cheng , Ying-Lang Wang
IPC分类号： C23G102
CPC分类号： H01L21/02063 , B08B1/00 , B08B3/04 , B08B3/12 , C11D7/265 , C11D11/0047 , H01L21/02074 , H01L21/67046 , H01L21/67057 , H01L21/67086 , Y10S134/902
摘要： A method of removing residual contamination including metal nitride particles from semiconductor wafer surfaces including the steps of: providing at least one semiconductor wafer with metal nitride particles adhering to the at least one semiconductor wafer surface thereto; subjecting the at least one semiconductor wafer to at least one mechanical brushing process while a cleaning solution including a carboxylic acid is supplied to at least one semiconductor wafer surface; and, subjecting the at least one semiconductor wafer to an a sonic cleaning process including the carboxylic acid cleaning solution.
摘要翻译：一种从半导体晶片表面去除包括金属氮化物颗粒的残留污染的方法，包括以下步骤：向至少一个半导体晶片提供附着在至少一个半导体晶片表面上的金属氮化物颗粒; 使至少一个半导体晶片进行至少一个机械刷洗过程，同时将包含羧酸的清洁溶液供应到至少一个半导体晶片表面; 以及对所述至少一个半导体晶片进行包括所述羧酸清洁溶液的声波清洁处理。

4. 发明申请

US20060189149A1 Method of smoothening dielectric layer 有权
公开(公告)号：US20060189149A1
公开(公告)日：2006-08-24
申请号：US11208612
申请日：2005-08-23
申请人： Wen-Long Lee , Jun Wu , Shih-Chi Lin , Chyi-Tsong Ni
发明人： Wen-Long Lee , Jun Wu , Shih-Chi Lin , Chyi-Tsong Ni
IPC分类号： H01L21/31
CPC分类号： H01L21/31051 , H01L21/31053
摘要： A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

5. 发明申请

US20060252258A1 Low temperature method for minimizing copper hillock defects 有权
标题翻译：用于最小化铜小丘缺陷的低温方法
公开(公告)号：US20060252258A1
公开(公告)日：2006-11-09
申请号：US11122393
申请日：2005-05-05
申请人： Jun Wu , Wen-Long Lee , Chyi-Tsong Ni , Shih-Chi Lin
发明人： Jun Wu , Wen-Long Lee , Chyi-Tsong Ni , Shih-Chi Lin
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/76801 , H01L21/76883
摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200 ° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).
摘要翻译：公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

6. 发明授权

US07851358B2 Low temperature method for minimizing copper hillock defects 有权
标题翻译：用于最小化铜小丘缺陷的低温方法
公开(公告)号：US07851358B2
公开(公告)日：2010-12-14
申请号：US11122393
申请日：2005-05-05
申请人： Jun Wu , Wen-Long Lee , Chyi-Tsong Ni , Shih-Chi Lin
发明人： Jun Wu , Wen-Long Lee , Chyi-Tsong Ni , Shih-Chi Lin
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/76801 , H01L21/76883
摘要： A method of fabricating a copper interconnect on a substrate is disclosed in which the interconnect and substrate are subjected to a low temperature anneal subsequent to polarization of the interconnect and prior to deposition of an overlying dielectric layer. The low temperature anneal inhibits the formation of hillocks in the copper material during subsequent high temperature deposition of the dielectric layer. Hillocks can protrude through passivation layer, thus causing shorts within the connections of the semiconductor devices formed on the substrate. In one example, the interconnect and substrate are annealed at a temperature of about 200° C. for a period of about 180 seconds in a forming gas environment comprising hydrogen (5 parts per hundred) and nitrogen (95 parts per hundred).
摘要翻译：公开了一种在衬底上制造铜互连的方法，其中互连和衬底在互连的极化之后并且在沉积上覆的电介质层之前经受低温退火。低温退火在随后的介电层的高温沉积期间抑制铜材料中的小丘的形成。小丘可以突出穿过钝化层，从而在形成在衬底上的半导体器件的连接之内引起短路。在一个实例中，在包含氢气（5份/百份）和氮气（95份/百份）的形成气体环境中，在大约200℃的温度下将互连和衬底退火约180秒的时间。

7. 发明授权

US07635651B2 Method of smoothening dielectric layer 有权
标题翻译：平滑电介质层的方法
公开(公告)号：US07635651B2
公开(公告)日：2009-12-22
申请号：US11208612
申请日：2005-08-23
申请人： Wen-Long Lee , Jun Wu , Shih-Chi Lin , Chyi-Tsong Ni
发明人： Wen-Long Lee , Jun Wu , Shih-Chi Lin , Chyi-Tsong Ni
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31051 , H01L21/31053
摘要： A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.
摘要翻译：一种平滑电介质层的方法。首先，提供基板。接下来，在半导体衬底上形成电介质层。最后，通过使用硅烷类气体和氮气体气体的等离子体处理使介电层平滑化。

8. 发明授权

US06436791B1 Method of manufacturing a very deep STI (shallow trench isolation) 有权
标题翻译：制造非常深的STI（浅沟槽隔离）的方法
公开(公告)号：US06436791B1
公开(公告)日：2002-08-20
申请号：US09880259
申请日：2001-06-14
申请人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
发明人： Shih-Chi Lin , Szu-An Wu , Ying-Lang Wang , Guey-Bao Huang
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation structure comprising the following steps. A substrate having an upper surface is provided. A pad oxide layer is formed upon the substrate. A nitride layer is formed over the pad oxide layer. The nitride layer having an upper surface. A trench is formed by etching the nitride layer, pad oxide layer and a portion of the substrate. The trench having a bottom and side walls. An oxide film is deposited upon the etched nitride layer surface, and the bottom and side walls of trench. The oxide film is removed from over the etched nitride layer surface, and the bottom of the trench to expose a portion of substrate within the trench. The removal of oxide film leaving oxide spacers over the trench side walls. Epitaxial silicon is selectively deposited over the exposed portion of substrate, filling the trench. A thermal oxide layer is formed over the epitaxial silicon, annealing the interface between the epitaxial silicon and the oxide spacers. The etched nitride layer and the oxide layer from over the etched substrate; and a portion of the oxide spacers extending above the surface of the etched substrate are removed, whereby the shallow trench isolation structure is formed within the trench.
摘要翻译：一种形成浅沟槽隔离结构的方法，包括以下步骤。提供具有上表面的基板。衬底氧化层形成在衬底上。在衬垫氧化物层上形成氮化物层。氮化物层具有上表面。通过蚀刻氮化物层，衬垫氧化物层和衬底的一部分来形成沟槽。沟槽具有底部和侧壁。在蚀刻的氮化物层表面和沟槽的底部和侧壁上沉积氧化物膜。从蚀刻的氮化物层表面上方的氧化膜和沟槽的底部去除氧化膜，以露出沟槽内的衬底的一部分。去除在沟槽侧壁上留下氧化物间隔物的氧化物膜。外延硅被选择性地沉积在衬底的暴露部分上，填充沟槽。在外延硅上形成热氧化层，退火外延硅与氧化物间隔物之间的界面。蚀刻的氮化物层和来自蚀刻的衬底上的氧化物层; 并且去除在蚀刻的衬底的表面上方延伸的氧化物间隔物的一部分，由此在沟槽内形成浅沟槽隔离结构。

9. 发明授权

US06815007B1 Method to solve IMD-FSG particle and increase Cp yield by using a new tougher UFUN season film 失效
标题翻译：通过使用新的更强的UFUN季节电影来解决IMD-FSG颗粒并增加Cp产量的方法
公开(公告)号：US06815007B1
公开(公告)日：2004-11-09
申请号：US10086258
申请日：2002-03-04
申请人： Ming-Hwa Yoo , Shih-Chi Lin , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
发明人： Ming-Hwa Yoo , Shih-Chi Lin , Yi-Lung Cheng , Szu-An Wu , Ying-Lang Wang
IPC分类号： C23C1622
CPC分类号： H01J37/32862 , C23C16/308 , C23C16/401 , C23C16/4404 , H01J2237/022
摘要： A method for reducing contaminants in a processing chamber having an inner wall by seasoning the walls. The method comprising the following steps. A first USG film is formed over the processing chamber inner wall. An FSG film is formed over the first USG film. A second USG film is formed over the FSG film. A nitrogen-containing film is formed over the second USG film wherein the first USG film, the FSG film, the second USG film and the nitrogen-containing film comprise a UFUN season film.

10. 发明授权

US06784077B1 Shallow trench isolation process 有权
标题翻译：浅沟槽隔离工艺
公开(公告)号：US06784077B1
公开(公告)日：2004-08-31
申请号：US10270973
申请日：2002-10-15
申请人： Shih-Chi Lin , Chih Chung Lee , Guey Bao Huang , Szu-An Wu , Ying Lang Wang , Chun Chun Yeh
发明人： Shih-Chi Lin , Chih Chung Lee , Guey Bao Huang , Szu-An Wu , Ying Lang Wang , Chun Chun Yeh
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming a silicon oxide, shallow trench isolation (STI) region, featuring a silicon rich, silicon oxide layer used to protect the STI region from a subsequent wet etch procedure, has been developed. The method features depositing a silicon oxide layer via PECVD procedures, without RF bias, using a high silane to oxygen ratio, resulting in a silicon rich, silicon oxide layer, located surrounding the STI region. The low etch rate of the silicon rich, silicon oxide layer, protect the silicon oxide STI region from buffered hydrofluoric wet etch procedures, used for removal of a dioxide pad layer.
摘要翻译：已经开发了一种形成氧化硅，浅沟槽隔离（STI）区域的方法，其特征在于用于保护STI区域免受后续湿蚀刻过程的富硅氧化硅层。该方法的特征是通过PECVD方法沉积氧化硅层，无需RF偏压，使用高硅烷与氧气比，导致位于STI区周围的富含硅的氧化硅层。富硅氧化硅层的低蚀刻速率保护硅氧化物STI区域免受用于去除二氧化物焊盘层的缓冲氢氟酸湿蚀刻工艺。

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