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1. 发明授权

US07470584B2 TEOS deposition method 有权
标题翻译： TEOS沉积法
公开(公告)号：US07470584B2
公开(公告)日：2008-12-30
申请号：US11040307
申请日：2005-01-21
申请人： Yi-Lung Cheng , Hong-Jui Chang , Ying-Lang Wang
发明人： Yi-Lung Cheng , Hong-Jui Chang , Ying-Lang Wang
IPC分类号： H01L21/31 , H01L21/469 , H01L21/8242
CPC分类号： H01L21/76801 , C23C16/401 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/02274 , H01L21/31612 , H01L21/7682 , H01L21/76837
摘要： A TEOS deposition method. A mixture of gases is introduced into a process chamber, in which the mixture of gases comprises tetra-ethyl-ortho-silicate (TEOS) and N2. Compressive stress of a TEOS oxide film is increased by activating the mixture of gases.
摘要翻译： TEOS沉积法。将气体混合物引入处理室，其中气体混合物包括四乙基原硅酸盐（TEOS）和N 2。通过激活气体混合物来增加TEOS氧化膜的压缩应力。

2. 发明申请

US20070267737A1 PACKAGED DEVICES AND METHODS FOR FORMING PACKAGED DEVICES 审中-公开
标题翻译：包装装置和形成包装装置的方法
公开(公告)号：US20070267737A1
公开(公告)日：2007-11-22
申请号：US11383922
申请日：2006-05-17
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng
IPC分类号： H01L23/15
CPC分类号： H01L23/3121 , H01L23/293 , H01L23/295 , H01L24/45 , H01L24/48 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/07802 , H01L2924/12041 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/00 , H01L2924/00015 , H01L2924/01029 , H01L2924/013 , H01L2924/00013 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Packaged devices and methods of forming packaged devices are provided. At least one device is disposed on a substrate. The material layer encapsulates the device and covers at least a portion of the substrate, wherein the material layer comprises at least a first portion adjacent to the device and a second portion over the first portion. The second portion has a thermal conductivity higher than a thermal conductivity of the first portion.
摘要翻译：提供了封装器件和形成封装器件的方法。至少一个装置设置在基板上。所述材料层封装所述装置并且覆盖所述基板的至少一部分，其中所述材料层包括至少邻近所述装置的第一部分和所述第一部分上的第二部分。第二部分具有高于第一部分的热导率的导热率。

3. 发明授权

US07176571B2 Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure 有权
标题翻译：氮化物阻挡层，以防止双重镶嵌结构中的金属（Cu）泄漏问题
公开(公告)号：US07176571B2
公开(公告)日：2007-02-13
申请号：US10753637
申请日：2004-01-08
申请人： Yi-Lung Cheng , Ying-Lung Wang
发明人： Yi-Lung Cheng , Ying-Lung Wang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76832 , H01L21/76807 , H01L21/76826
摘要： A method for forming a composite barrier layer that also functions as an etch stop in a damascene process is disclosed. A SiC layer is deposited on a substrate in a CVD process chamber followed by deposition of a silicon nitride layer to complete the composite barrier layer. The SiC layer exhibits excellent adhesion to a copper layer in the substrate and is formed by a method that avoids reactive Si+4 species and thereby prevents CuSiX formation. The silicon nitride layer thickness is sufficient to provide superior barrier capability to metal ions but is kept as thin as possible to minimize the dielectric constant of the composite barrier layer. The composite barrier layer provides excellent resistance to copper oxidation during oxygen ashing steps and enables a copper layer to be fabricated with a lower leakage current than when a conventional silicon nitride barrier layer is employed.
摘要翻译：公开了一种用于形成复合阻挡层的方法，该复合阻挡层也用作镶嵌工艺中的蚀刻停止。将SiC层沉积在CVD处理室中的衬底上，随后沉积氮化硅层以完成复合势垒层。 SiC层对衬底中的铜层表现出优异的粘附性，并且通过避免反应性Si + 4+物质并由此防止CuSi X X形成的方法形成。氮化硅层的厚度足以为金属离子提供优异的阻挡能力，但保持尽可能的薄，以使复合阻挡层的介电常数最小化。复合阻挡层在氧化灰化步骤期间提供优异的铜氧化性能，并且与使用常规氮化硅阻挡层相比，能够以较低的漏电流制造铜层。

4. 发明授权

US07157367B2 Device structure having enhanced surface adhesion and failure mode analysis 有权
标题翻译：具有增强的表面粘附和破坏模式分析的装置结构
公开(公告)号：US07157367B2
公开(公告)日：2007-01-02
申请号：US10861149
申请日：2004-06-04
申请人： Hway Chi Lin , Yi-Lung Cheng , Chao-Hsiung Wang
发明人： Hway Chi Lin , Yi-Lung Cheng , Chao-Hsiung Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L2924/0002 , H01L2924/00
摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).
摘要翻译：提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

5. 发明授权

US07078336B2 Method and system for fabricating a copper barrier layer with low dielectric constant and leakage current 有权
标题翻译：具有低介电常数和漏电流的铜阻挡层的制造方法和系统
公开(公告)号：US07078336B2
公开(公告)日：2006-07-18
申请号：US10716818
申请日：2003-11-19
申请人： Yi-Lung Cheng , Ying-Lang Wang
发明人： Yi-Lung Cheng , Ying-Lang Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76831
摘要： A method is disclosed for reducing metal diffusion in a semiconductor device. After forming a first metal portion over a substrate, a silicon carbon nitro-oxide (SiCNO) layer is deposited on the first metal portion. A dielectric layer is deposited over the SiCNO layer, and an opening is generated in the SiCNO layer and the dielectric layer for a second metal portion to be connected to the first metal portion, wherein the SiCNO layer reduces the diffusion of the first metal portion into the dielectric layer.
摘要翻译：公开了一种用于减少半导体器件中的金属扩散的方法。在衬底上形成第一金属部分之后，在第一金属部分上沉积硅碳氧化物（SiCNO）层。在SiCNO层上沉积介电层，在SiCNO层和第二金属部分的介电层上产生开口以连接到第一金属部分，其中SiCNO层将第一金属部分的扩散减少到电介质层。

6. 发明申请

US20060076694A1 Semiconductor device package with concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency 审中-公开
标题翻译：半导体器件封装，具有凹陷封装体，防止器件分层，提高热传输效率
公开(公告)号：US20060076694A1
公开(公告)日：2006-04-13
申请号：US10962478
申请日：2004-10-13
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Yi-Lung Cheng
IPC分类号： H01L23/28
CPC分类号： H01L23/3135 , H01L23/3121 , H01L23/367 , H01L24/48 , H01L2224/451 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/0102 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor device package has a concavity-containing encapsulation body to prevent device delamination and increase thermal-transferring efficiency. An encapsulation body of polymer-based material encapsulates a semiconductor device and bonding wires, and a concavity structure is patterned on the encapsulation body by imprinting, laser drilling, photolithography, dry etching, die sawing, or other surface patterning technologies.
摘要翻译：半导体器件封装具有含凹入的封装体，以防止器件分层并提高热传递效率。基于聚合物的材料的封装体封装半导体器件和接合线，并且通过压印，激光钻孔，光刻，干法蚀刻，模切或其它表面图案化技术在封装体上图案化凹形结构。

7. 发明申请

US20060051973A1 Method for forming IMD films 有权
标题翻译：形成IMD膜的方法
公开(公告)号：US20060051973A1
公开(公告)日：2006-03-09
申请号：US10937215
申请日：2004-09-09
申请人： Yi-Lung Cheng , Miao-Cheng Liao , Ying-Lang Wang
发明人： Yi-Lung Cheng , Miao-Cheng Liao , Ying-Lang Wang
IPC分类号： H01L21/469
CPC分类号： H01L21/76807
摘要： A method for forming IMD films. A substrate is provided. A plurality of dielectric films are formed on the substrate, wherein each of the dielectric layers are deposited in-situ in one chamber with only one thermal cycle.
摘要翻译：一种形成IMD膜的方法。提供基板。在基板上形成多个电介质膜，其中每个电介质层原位沉积在仅具有一个热循环的一个室中。

8. 发明授权

US06979656B2 Carbon and halogen doped silicate glass dielectric layer and method for fabricating the same 失效
标题翻译：碳和卤素掺杂的硅酸盐玻璃介电层及其制造方法
公开(公告)号：US06979656B2
公开(公告)日：2005-12-27
申请号：US10729217
申请日：2003-12-04
申请人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
发明人： Shiu-Ko Jangjian , Jun Wu , Chi-Wen Liu , Ying-Lung Wang , Yi-Lung Cheng , Michael Chang , Szu-An Wu
IPC分类号： H01L21/31 , H01L21/316 , H01L21/76 , H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , C23C16/401 , H01L21/02126 , H01L21/02131 , H01L21/02211 , H01L21/02274 , H01L21/31629 , H01L21/31633 , H01L21/76802 , H01L21/76807 , H01L21/76835 , H01L21/7684 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a dielectric layer provides for use of a carbon source material separate from a halogen source material when forming a carbon and halogen doped silicate glass dielectric layer. The use of separate carbon and halogen source materials provides enhanced process latitude when forming the carbon and halogen doped silicate glass dielectric layer. Such a carbon and halogen doped silicate glass dielectric layer having a dielectric constant greater than about 3.0 is particularly useful as an intrinsic planarizing stop layer within a damascene method. A bilayer dielectric layer construction comprising a carbon and halogen doped silicate glass and a carbon doped silicate glass dielectric layer absent halogen doping is useful within a dual damascene method.
摘要翻译：制造电介质层的方法提供了当形成碳和卤素掺杂的硅酸盐玻璃介电层时与卤素源材料分开的碳源材料的使用。当形成碳和卤素掺杂的硅酸盐玻璃介电层时，使用单独的碳和卤素源材料提供了增强的工艺自由度。具有大于约3.0的介电常数的这种碳和卤素掺杂的硅酸盐玻璃介电层特别适用于镶嵌法中的本征平面化停止层。包含碳和卤素掺杂的硅酸盐玻璃的双层电介质层结构和不含卤素掺杂的碳掺杂的硅酸盐玻璃介电层在双镶嵌方法中是有用的。

9. 发明授权

US06903019B2 CMP process leaving no residual oxide layer or slurry particles 失效
标题翻译： CMP工艺不留下残留的氧化物层或浆料颗粒
公开(公告)号：US06903019B2
公开(公告)日：2005-06-07
申请号：US10706495
申请日：2003-11-12
申请人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
发明人： Ying-Lang Wang , Shih-Chi Lin , Yi-Lung Cheng , Chi-Wen Liu , Ming-Hua Yoo , Wen-Kung Cheng , Jiann-Kwang Wang
IPC分类号： C09G1/02 , H01L21/321 , H01L21/768 , H01L21/461
CPC分类号： C09G1/02 , H01L21/3212 , H01L21/7684
摘要： Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.
摘要翻译：当前执行的CMP中看到的两个问题是浆料颗粒保留在表面上并形成最后一层氧化物的倾向。这些问题已经通过向浆料中加入一定量的TMAH或TBAH来解决。这具有使表面被抛光的疏水性的效果。在该状态下，在CMP结束时，残留的氧化层不会残留在表面上。许多浆料磨料颗粒也不会保持粘附到新鲜抛光的表面。那些可以通过简单的冲洗或抛光容易地去除。作为替代方案，CMP工艺可以在三个阶段进行 - 第一个惯例CMP，然后在TMAH或TBAH的溶液中抛光，最后进行温和的冲洗或抛光。

10. 发明授权

US06759347B1 Method of forming in-situ SRO HDP-CVD barrier film 失效
标题翻译：形成原位SRO HDP-CVD阻挡膜的方法
公开(公告)号：US06759347B1
公开(公告)日：2004-07-06
申请号：US10401715
申请日：2003-03-27
申请人： Yi-Lung Cheng , Ming-Hwa Yoo , Sze-An Wu , Ying Lung Wang
发明人： Yi-Lung Cheng , Ming-Hwa Yoo , Sze-An Wu , Ying Lung Wang
IPC分类号： H01L2131
CPC分类号： C23C16/505 , C23C16/401 , H01L21/31629 , H01L21/76819 , H01L21/76829
摘要： A method of reducing plasma induced damage in semiconductor devices and fluorine damage to a metal containing layer including providing a semiconductor wafer including semiconductor devices including a gate oxide and a process surface including metal lines; carrying out a first high density plasma chemical vapor deposition (HDP-CVD) process to controllably produce a silicon rich oxide (SRO) layer including a relatively increased thickness at a center portion of the process surface compared to a peripheral portion of the process surface; and, carrying out a second HDP-CVD process in-situ to deposit a fluorine doped silicon dioxide layer over the SRO layer to fill a space between the metal lines.
摘要翻译：一种降低半导体器件中的等离子体诱发损伤的方法和对含金属层的氟损伤的方法，包括提供包括包括栅极氧化物的半导体器件和包括金属线的工艺表面的半导体晶片的半导体晶片; 执行第一高密度等离子体化学气相沉积（HDP-CVD）工艺，以可控地产生富硅氧化物（SRO）层，其与过程表面的周边部分相比在工艺表面的中心部分包括相对增加的厚度; 并且原位进行第二HDP-CVD工艺以在SRO层上沉积氟掺杂的二氧化硅层以填充金属线之间的空间。

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