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1. 发明授权

US06475555B2 Process for screening features on an electronic substrate with a low viscosity paste 有权
标题翻译：用低粘度糊剂在电子基片上筛选特征的方法
公开(公告)号：US06475555B2
公开(公告)日：2002-11-05
申请号：US09429256
申请日：1999-10-29
申请人： Jon A. Casey , Dinesh Gupta , Lester Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Brenda L. Peterson , Robert A. Rita
发明人： Jon A. Casey , Dinesh Gupta , Lester Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Brenda L. Peterson , Robert A. Rita
IPC分类号： B05D132
CPC分类号： H05K3/1233 , H01L21/4867 , H01L23/49883 , H01L2924/0002 , H01L2924/09701 , H05K1/092 , H05K3/227 , H05K2201/0116 , H05K2203/0783 , H01L2924/00
摘要： A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.
摘要翻译：一种方法，其中将低粘度的含金属浆料筛选到陶瓷毛坯上，然后设置以增加其粘度。在一种方法中，低粘度是由过量的溶剂引起的，然后将其印迹或以其它方式除去，使得糊料的粘度增加。在另一种方法中，低粘度糊剂含有交联剂，其使糊剂在筛选后增加其粘度。

2. 发明授权

US06231707B1 Method of forming a multilayer ceramic substrate with max-punched vias 失效
标题翻译：形成具有最大冲孔的多孔陶瓷基板的方法
公开(公告)号：US06231707B1
公开(公告)日：2001-05-15
申请号：US09158615
申请日：1998-09-22
申请人： Dinesh Gupta , L. Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Robert A. Rita
发明人： Dinesh Gupta , L. Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Robert A. Rita
IPC分类号： B32B3126
CPC分类号： H05K3/4061 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K3/4611 , H05K3/4629 , H05K2201/09063 , H05K2201/096 , H05K2201/09609 , H05K2203/308 , Y10T156/1056 , H01L2924/00
摘要： In the formation of multilayer ceramic substrates, greensheets are utilized which have the same pattern and number of vias punched in each greensheet. Then, selected vias may be filled with metallic paste to form the internal connections of the multilayer ceramic substrate. The remaining vias may be filled with a fugitive material or left totally unfilled. Also disclosed is the multilayer ceramic substrate produced by this method.
摘要翻译：在多层陶瓷基板的形成中，使用具有与每个毛坯中冲孔相同的图案和数量的通孔的刮板。然后，可以用金属浆料填充所选择的通孔，以形成多层陶瓷基板的内部连接。其余的通孔可能充满了一种逃逸材料，或者完全没有填充。还公开了通过该方法制造的多层陶瓷基板。

3. 发明授权

US06413339B1 Low temperature sintering of ferrite materials 失效
标题翻译：铁氧体材料的低温烧结
公开(公告)号：US06413339B1
公开(公告)日：2002-07-02
申请号：US09470457
申请日：1999-12-22
申请人： Govindarajan Natarajan , Jon A. Casey , Martin E. Klepeis , John U. Knickerbocker , Srinivasa S. N. Reddy , Robert A. Rita , Subhash L. Shinde
发明人： Govindarajan Natarajan , Jon A. Casey , Martin E. Klepeis , John U. Knickerbocker , Srinivasa S. N. Reddy , Robert A. Rita , Subhash L. Shinde
IPC分类号： B32B3116
CPC分类号： C04B35/2683 , C04B35/64 , H01F1/0027 , H01F41/0253 , Y10T156/1056 , Y10T156/1057
摘要： The present invention relates generally to a new metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.
摘要翻译：本发明一般涉及具有通孔的新的金属/磁陶瓷层压体及其工艺。更具体地，本发明包括用于制造具有大量孔的大面积陶瓷层压体磁体的新方法，用于电子和电子束控制的集成金属板和共烧结电极。本发明还涉及磁矩阵显示器（MMD）和电子束源，及其制造方法。

4. 发明授权

US06916670B2 Electronic package repair process 失效
标题翻译：电子封装修复过程
公开(公告)号：US06916670B2
公开(公告)日：2005-07-12
申请号：US10358431
申请日：2003-02-04
申请人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
发明人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
IPC分类号： H05K3/46 , H01L21/48 , H01L23/12 , H01L23/498 , H05K1/03 , H05K3/00 , H05K3/22 , H01L21/00
CPC分类号： H05K3/225 , H01L21/4846 , H01L23/49811 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/0029 , H05K3/4629 , H05K2203/173 , Y10T29/49124 , Y10T29/49135 , H01L2924/00
摘要： A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.
摘要翻译：一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。有缺陷的网和修复网各自终止在基板的表面通孔处。使用激光器在基板上和基板上形成点火电路。之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

5. 发明授权

US06823585B2 Method of selective plating on a substrate 失效
标题翻译：在基板上选择性镀覆的方法
公开(公告)号：US06823585B2
公开(公告)日：2004-11-30
申请号：US10249305
申请日：2003-03-28
申请人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
发明人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
IPC分类号： H01R4300
CPC分类号： H05K3/242 , H05K1/0306 , H05K3/0035 , H05K3/048 , H05K3/184 , H05K3/225 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49158 , Y10T29/49163 , Y10T29/49165 , Y10T29/49171 , Y10T29/49172 , Y10T29/49721 , Y10T29/49732 , Y10T29/49737 , Y10T29/49746
摘要： A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.
摘要翻译：在基板上形成表面电镀金属化的方法和结构。将两层胶带施加到基材的表面。通过暴露衬底表面的两层带切割第一路径。第一路径在衬底的顶表面上连接至少一个导电通孔。通过暴露第一层胶带的第二层胶带切割第二条路径。第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。去除胶带时，去除牺牲路径。

6. 发明授权

US07294909B2 Electronic package repair process 有权
标题翻译：电子封装修复过程
公开(公告)号：US07294909B2
公开(公告)日：2007-11-13
申请号：US11099161
申请日：2005-04-05
申请人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
发明人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H05K3/225 , H01L21/4846 , H01L23/49811 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/0029 , H05K3/4629 , H05K2203/173 , Y10T29/49124 , Y10T29/49135 , H01L2924/00
摘要： A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.
摘要翻译：一种多层陶瓷修复工艺，提供了一个新的电气修复路径，以连接顶面通孔。修复路径是建立在有缺陷的网和包含在多层陶瓷基板内的冗余修复网之间。有缺陷的网和修复网各自终止在基板的表面通孔处。使用激光器在基板上和基板上形成点火电路。之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

7. 发明授权

US06461493B1 Decoupling capacitor method and structure using metal based carrier 有权
标题翻译：使用金属载体去耦电容器的方法和结构
公开(公告)号：US06461493B1
公开(公告)日：2002-10-08
申请号：US09472136
申请日：1999-12-23
申请人： Mukta S. Farooq , Shaji Farooq , John U. Knickerbocker , Robert A. Rita , Srinivasa N. Reddy
发明人： Mukta S. Farooq , Shaji Farooq , John U. Knickerbocker , Robert A. Rita , Srinivasa N. Reddy
IPC分类号： C25D502
CPC分类号： H05K3/445 , H01G4/10 , H05K1/053 , H05K1/162 , H05K3/4069 , H05K2201/09554 , H05K2203/0315 , H05K2203/1142
摘要： A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.
摘要翻译：一种使用金属载体制造结构并形成双电容器结构的方法。该工艺包括形成通过金属载体的第一通孔，在金属载体周围形成电介质层，并在第一通孔内部形成介电层，形成穿过电介质层和金属载体的第二通孔，并填充至少一个通孔孔与导电材料。在一个优选实施例中，该方法还包括在形成电介质层之前通过金属载体形成第三通孔，其中介电层围绕金属载体形成在第一通孔的内部，以及在第三通孔的内部。第一通孔，第二通孔和第三通孔均填充有导电材料。在一个优选实施例中，电介质层包括与底表面相对的顶表面，并且在介电层的顶表面和底表面中的至少一个上形成电极。

8. 发明授权

US6023407A Structure for a thin film multilayer capacitor 失效
标题翻译：薄膜多层电容器的结构
公开(公告)号：US6023407A
公开(公告)日：2000-02-08
申请号：US31235
申请日：1998-02-26
申请人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
IPC分类号： H01L27/04 , H01G4/30 , H01G4/33 , H01L21/02 , H01L21/822 , H01G4/005 , H01G4/228
CPC分类号： H01L28/40 , H01G4/306 , Y10T29/435
摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 .mu.m thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 .mu.m for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译：提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。还提出了一种用于制造中介层薄膜电容器的方法。为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10μm的厚的第一金属层沉积在衬底上然后施加剩余的薄膜，包括电介质膜和第二金属层。第一金属层包括Pt或其它电极金属，或Pt，Cr和Cu金属的组合以及扩散阻挡层。另外的Ti层可以用于附着增强。对于Cr层，第一金属层的厚度约为：200A; Cu层为0.5-10μm; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。

9. 发明授权

US06216324B1 Method for a thin film multilayer capacitor 失效
标题翻译：薄膜多层电容器的方法
公开(公告)号：US06216324B1
公开(公告)日：2001-04-17
申请号：US09382536
申请日：1999-08-25
申请人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人： Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
IPC分类号： H01G4002
CPC分类号： H01L28/40 , H01G4/306 , Y10T29/435
摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译：提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。还提出了一种用于制造中介层薄膜电容器的方法。为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10毫米的厚的第一金属层沉积在衬底上，衬底上沉积然后施加包括电介质膜和第二金属层的剩余薄膜。第一金属层由Pt或其他电极金属或Pt，Cr和Cu金属的组合以及扩散阻挡层组成。另外的Ti层可以用于附着增强。对于Cr层，第一金属层的厚度约为：200A; 铜层为0.5-10毫米; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。

10. 发明授权

US06339527B1 Thin film capacitor on ceramic 失效
标题翻译：陶瓷薄膜电容器
公开(公告)号：US06339527B1
公开(公告)日：2002-01-15
申请号：US09470456
申请日：1999-12-22
申请人： Mukta S. Farooq , John U. Knickerbocker , Srinivasa S. N. Reddy , Robert A. Rita , Roy Yu
发明人： Mukta S. Farooq , John U. Knickerbocker , Srinivasa S. N. Reddy , Robert A. Rita , Roy Yu
IPC分类号： H01G4008
CPC分类号： H01L28/40 , H01L21/31683
摘要： The capacitor on a ceramic substrate one by unique film metallization including in one embodiment an in situ oxidation of titanium to create a metal oxide capacitor. The combination of metals when used with the appropriate optimized oxidation conditions and parameters ensures a high yielding capacitor with high capacitance in absence of noble metals and with ease of manufacture providing a low cost, high yield capacitor on ceramic.
摘要翻译：陶瓷衬底上的电容器通过独特的膜金属化，包括在一个实施方案中，原位氧化钛以产生金属氧化物电容器。当与适当的优化氧化条件和参数一起使用时，金属的组合确保了在不存在贵金属的情况下具有高电容的高产电容器，并且易于制造，在陶瓷上提供低成本，高产率的电容器。

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