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1. 发明授权

US06475555B2 Process for screening features on an electronic substrate with a low viscosity paste 有权
标题翻译：用低粘度糊剂在电子基片上筛选特征的方法
公开(公告)号：US06475555B2
公开(公告)日：2002-11-05
申请号：US09429256
申请日：1999-10-29
申请人： Jon A. Casey , Dinesh Gupta , Lester Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Brenda L. Peterson , Robert A. Rita
发明人： Jon A. Casey , Dinesh Gupta , Lester Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Brenda L. Peterson , Robert A. Rita
IPC分类号： B05D132
CPC分类号： H05K3/1233 , H01L21/4867 , H01L23/49883 , H01L2924/0002 , H01L2924/09701 , H05K1/092 , H05K3/227 , H05K2201/0116 , H05K2203/0783 , H01L2924/00
摘要： A process wherein a low viscosity, metal-containing paste is screened onto a ceramic greensheet and then sets up to increase its viscosity. In one method, the low viscosity is caused by excess solvent which is then blotted or otherwise removed so that the viscosity of the paste is increased. In an alternative method, the low viscosity paste contains a cross-linking agent which causes the paste to increase its viscosity after screening.
摘要翻译：一种方法，其中将低粘度的含金属浆料筛选到陶瓷毛坯上，然后设置以增加其粘度。在一种方法中，低粘度是由过量的溶剂引起的，然后将其印迹或以其它方式除去，使得糊料的粘度增加。在另一种方法中，低粘度糊剂含有交联剂，其使糊剂在筛选后增加其粘度。

2. 发明授权

US06341417B1 Pre-patterned substrate layers for being personalized as needed 有权
标题翻译：根据需要进行个性化的预先图案化的衬底层
公开(公告)号：US06341417B1
公开(公告)日：2002-01-29
申请号：US09404510
申请日：1999-09-23
申请人： Dinesh Gupta , Lester Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Keith C. O'Neil , Brenda L. Peterson
发明人： Dinesh Gupta , Lester Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Keith C. O'Neil , Brenda L. Peterson
IPC分类号： H05K336
CPC分类号： H01L23/5382 , H01L2924/0002 , H05K1/0287 , H05K1/0298 , H05K1/0306 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method and structure for personalizing a multi-layer substrate structure includes supplying a generic layer having electrical features and altering the electrical features to produce a personalized layer of the multi-layer substrate.
摘要翻译：用于个性化多层衬底结构的方法和结构包括提供具有电特征并改变电特征的通用层以产生多层衬底的个性化层。

3. 发明授权

US06231707B1 Method of forming a multilayer ceramic substrate with max-punched vias 失效
标题翻译：形成具有最大冲孔的多孔陶瓷基板的方法
公开(公告)号：US06231707B1
公开(公告)日：2001-05-15
申请号：US09158615
申请日：1998-09-22
申请人： Dinesh Gupta , L. Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Robert A. Rita
发明人： Dinesh Gupta , L. Wynn Herron , John U. Knickerbocker , David C. Long , Jawahar P. Nayak , Robert A. Rita
IPC分类号： B32B3126
CPC分类号： H05K3/4061 , H01L21/486 , H01L23/49827 , H01L2924/0002 , H05K1/0306 , H05K3/4611 , H05K3/4629 , H05K2201/09063 , H05K2201/096 , H05K2201/09609 , H05K2203/308 , Y10T156/1056 , H01L2924/00
摘要： In the formation of multilayer ceramic substrates, greensheets are utilized which have the same pattern and number of vias punched in each greensheet. Then, selected vias may be filled with metallic paste to form the internal connections of the multilayer ceramic substrate. The remaining vias may be filled with a fugitive material or left totally unfilled. Also disclosed is the multilayer ceramic substrate produced by this method.
摘要翻译：在多层陶瓷基板的形成中，使用具有与每个毛坯中冲孔相同的图案和数量的通孔的刮板。然后，可以用金属浆料填充所选择的通孔，以形成多层陶瓷基板的内部连接。其余的通孔可能充满了一种逃逸材料，或者完全没有填充。还公开了通过该方法制造的多层陶瓷基板。

4. 发明授权

US5480503A Process for producing circuitized layers and multilayer ceramic sub-laminates and composites thereof 失效
标题翻译：用于制造电路层的方法和多层陶瓷副叠层及其复合材料
公开(公告)号：US5480503A
公开(公告)日：1996-01-02
申请号：US175727
申请日：1993-12-30
申请人： Jon A. Casey , David B. Goland , Dinesh Gupta , Lester W. Herron , James N. Humenik , Thomas E. Lombardi , John U. Knickerbocker , Robert J. Sullivan , James R. Wylder
发明人： Jon A. Casey , David B. Goland , Dinesh Gupta , Lester W. Herron , James N. Humenik , Thomas E. Lombardi , John U. Knickerbocker , Robert J. Sullivan , James R. Wylder
IPC分类号： H01L21/48 , H01L21/68 , H01L23/538 , H05K1/03 , H05K3/20 , H05K3/40 , H05K3/46 , B32B31/04 , B32B31/12 , B32B31/26 , B32B31/28
CPC分类号： H01L21/568 , H01L21/4857 , H01L21/6835 , H01L23/5383 , H01L23/5385 , H05K3/20 , H05K3/4061 , H05K3/4617 , H05K3/4629 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , Y10T156/1056 , Y10T156/1142 , Y10T29/49126 , Y10T29/49128
摘要： Process for producing circuitized greensheets including multi-layer ceramic sub-laminates and composites comprising thin ceramic greensheets carrying and thin, fine line patterned conductive metal layers. The invention comprises releasably-supporting the thin greensheets on a temporary carrier support having an ablatable release layer, preferably over a patterned conductive layer, and filling the vias with conductive metal paste, whereby the thin greensheets are supported against warpage and distortion. The supported greensheets are formed as single layers, pairs and stacks thereof, as desired, and thereafter separated from the temporary support for use.
摘要翻译：用于生产包括多层陶瓷亚层压板和复合材料的电路化滤纸的方法，该复合材料包括载有薄的陶瓷片材和薄的精细线图案化的导电金属层。本发明包括在具有可消融脱模层的临时载体支撑件上可释放地支撑薄片，优选地在图案化的导电层之上，并且用导电金属浆料填充该通孔，从而支撑薄的薄片以防止翘曲和变形。支撑的格子根据需要形成为单层，成对和堆叠，然后与临时支撑件分离使用。

5. 发明授权

US08089133B2 Optical assemblies for transmitting and manipulating optical beams 有权
标题翻译：用于传输和操纵光束的光学组件
公开(公告)号：US08089133B2
公开(公告)日：2012-01-03
申请号：US10993305
申请日：2004-11-19
申请人： Dinesh Gupta , Brenda L. Peterson , Mark V. Pierson , Eugen Schenfeld , Subhash L. Shinde
发明人： Dinesh Gupta , Brenda L. Peterson , Mark V. Pierson , Eugen Schenfeld , Subhash L. Shinde
IPC分类号： H01L31/0232
CPC分类号： G02B6/3522 , G02B6/2817 , G02B6/3544 , G02B6/3574 , G02B6/3598 , G02B6/4214 , G02B6/4244 , G02B6/4245 , G02B6/4246 , G02B6/4249 , G02B6/4259 , G02B6/4269 , G02B6/4281 , G02B6/43 , H01L2924/0002 , H01L2924/00
摘要： Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.
摘要翻译：提供用于引导光束的光学立方体和光学立方体组件。光学立方体是可以适于反射，透射和/或部分地反射和透射光束的光学透明模块。光学立方体可以包括用于引导光束的双向或多方向光束引导元件。光学立方体组件可以包括附接到光学立方体的柔性芯片组件。芯片组件可以包括用于发射光束的垂直腔表面发射激光器或用于接收安装在柔性和电互连安装组件上的光束的接收器。

6. 发明授权

US06836015B2 Optical assemblies for transmitting and manipulating optical beams 失效
标题翻译：用于传输和操纵光束的光学组件
公开(公告)号：US06836015B2
公开(公告)日：2004-12-28
申请号：US10428960
申请日：2003-05-02
申请人： Monty M. Denneau , Dinesh Gupta , Lisa J. Jimarez , Steven Ostrander , Brenda L. Peterson , Mark V. Pierson , Eugen Schenfeld , Subhash L. Shinde
发明人： Monty M. Denneau , Dinesh Gupta , Lisa J. Jimarez , Steven Ostrander , Brenda L. Peterson , Mark V. Pierson , Eugen Schenfeld , Subhash L. Shinde
IPC分类号： H01L2334
CPC分类号： G02B6/3522 , G02B6/2817 , G02B6/3544 , G02B6/3574 , G02B6/3598 , G02B6/4214 , G02B6/4244 , G02B6/4245 , G02B6/4246 , G02B6/4249 , G02B6/4259 , G02B6/4269 , G02B6/4281 , G02B6/43 , H01L2924/0002 , H01L2924/00
摘要： Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.
摘要翻译：提供用于引导光束的光学立方体和光学立方体组件。光学立方体是可以适于反射，透射和/或部分地反射和透射光束的光学透明模块。光学立方体可以包括用于引导光束的双向或多方向光束引导元件。光学立方体组件可以包括附接到光学立方体的柔性芯片组件。芯片组件可以包括用于发射光束的垂直腔表面发射激光器或用于接收安装在柔性和电互连安装组件上的光束的接收器。

7. 发明授权

US5601672A Method for making ceramic substrates from thin and thick ceramic greensheets 失效
标题翻译：从薄而厚的陶瓷板制造陶瓷基板的方法
公开(公告)号：US5601672A
公开(公告)日：1997-02-11
申请号：US333010
申请日：1994-11-01
申请人： Jon A. Casey , Dinesh Gupta , James R. Wylder
发明人： Jon A. Casey , Dinesh Gupta , James R. Wylder
IPC分类号： C04B35/111 , C04B35/622 , H01L21/48 , H01L23/538 , H05K1/03 , H05K3/40 , H05K3/46 , B32B31/12 , B32B31/26
CPC分类号： H05K3/4629 , C04B35/111 , C04B35/62218 , H01L21/4857 , H01L23/5383 , H05K3/462 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2203/063 , H05K3/4061 , H05K3/4623 , Y10T156/1056 , Y10T29/49163
摘要： Method for producing ceramic laminates from a plurality of greensheet layers which include one or more thin greensheet layers, e.g. having a thickness less than about 3 mils, with interposed patterned circuit layers and conductive vias, while avoiding the loss of strength and the distortion encountered when paste compositions are pre-applied to such thin greensheet layers. The invention avoids the aforementioned problems by the use of a plurality of greensheet layers including thicker, paste-resistant greensheet layers having a thickness greater than the thin greensheet layer, e.g., between 5 and 10 mils, each pair of the thicker greensheet layers confining therebetween an unscreened thin greensheet layer, one of the thicker greensheet layers also being screened with the circuit pattern layer normally applied to the interposed thin greensheet layer. Thereafter the superposed layers are laminated and sintered to form the composite.
摘要翻译：用于从多个毛坯层制造陶瓷层压板的方法，所述多个毛坯层包括一个或多个薄的毛坯层，例如，具有小于约3密耳的厚度，具有插入的图案化电路层和导电通孔，同时避免了当将糊剂组合物预先施加到这种薄的毛坯层时遇到的强度损失和失真。本发明通过使用多个毛坯层来避免上述问题，所述多个毛坯层包括厚度大于薄的毛坯层的厚度较大的耐膏状毛坯层，例如在5至10密耳之间，每对较厚的毛坯层限制在它们之间未筛选的薄毛坯层，较厚的毛坯层之一也被通常施加到插入的薄毛坯层上的电路图案层进行筛选。然后将叠层层压并烧结以形成复合材料。

8. 发明授权

US06713686B2 Apparatus and method for repairing electronic packages 失效
标题翻译：用于修理电子封装的装置和方法
公开(公告)号：US06713686B2
公开(公告)日：2004-03-30
申请号：US10053362
申请日：2002-01-18
申请人： Wiren D. Becker , Dinesh Gupta , Sudipta K. Ray , Robert A. Rita , Herbert I. Stoller , Kathleen M. Wiley
发明人： Wiren D. Becker , Dinesh Gupta , Sudipta K. Ray , Robert A. Rita , Herbert I. Stoller , Kathleen M. Wiley
IPC分类号： H01R1204
CPC分类号： H01L23/5382 , H01L2924/0002 , H01L2924/09701 , H05K1/0292 , H05K1/113 , Y10T29/49155 , H01L2924/00
摘要： A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.
摘要翻译：多芯片模块基板，其布置有在模块的芯片位置的修复通道之间延伸的修理通孔和修复线，通过该维修线可以进行修理以克服模块电路中的缺陷，以及用于实现该电路中的缺陷的修复的方法模块。在第一信号通孔，第二信号通孔以及在第一信号通孔和第二信号通孔之间延伸并且用于电连接第一信号通孔的电路线中的任何一个中可能会发生缺陷。识别出故障电路后，电路的信号通孔被隔离。然后，故障电路的第一信号通路经由具有第一信号的芯片位置的修复通孔经由与具有第二信号通路的芯片位置的修复通路连接，并且具有缺陷电路的第二信号通孔电路经由具有第二信号的芯片位置的修复通路经由与经由具有第一信号通孔的芯片位置的修复通路相连接。

9. 发明授权

US07926011B1 System and method of generating hierarchical block-level timing constraints from chip-level timing constraints 有权
标题翻译：从芯片级定时约束产生分级块级时序约束的系统和方法
公开(公告)号：US07926011B1
公开(公告)日：2011-04-12
申请号：US11621915
申请日：2007-01-10
申请人： Oleg Levitsky , Chien-Chu Kuo , Dinesh Gupta
发明人： Oleg Levitsky , Chien-Chu Kuo , Dinesh Gupta
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/505 , G06F2217/84
摘要： A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.
摘要翻译：一种设计集成电路的系统和方法，该集成电路能够导出从芯片级定时约束和分析导出的集成电路的各个块级电路的时序约束。块级定时约束是块级电路的输入和输出端口处的一个或多个逻辑时序约束点的形式。每个逻辑时序约束点指定用于通过端口对数据进行时钟源的时钟源，从输入端口向后指定数据传播延迟并从输出端口转发的延迟参数以及与数据路径相关联的任何定时异常。使用逻辑时序约束点，电路设计系统对每个块级电路进行独立的时序分析和优化。然后，系统将块级电路重新组装成可以实现时序闭合的修改的芯片级电路。

10. 发明授权

US07672315B2 Methods and apparatus for deskewing VCAT/LCAS members 有权
标题翻译：用于偏移VCAT / LCAS成员的方法和设备
公开(公告)号：US07672315B2
公开(公告)日：2010-03-02
申请号：US11210127
申请日：2005-08-23
申请人： Dinesh Gupta , Dev Shankar Mukherjee , Rakesh Kumar Malik
发明人： Dinesh Gupta , Dev Shankar Mukherjee , Rakesh Kumar Malik
IPC分类号： H04L12/56
CPC分类号： H04J3/0623 , H04J3/1611 , H04J2203/0094
摘要： Write logic and read logic are coupled to SDRAM and a frame status table. VCG members are written into SDRAM by the write logic and an entry (based on the MFI and SQ) in the frame status table is maintained by the write logic for each member. The read logic scans the frame status table to identify the earliest frame number for which data is available in SDRAM. Based on the frame status and the address pointer offset, the read logic maintains a state table entry for each VCG member and a state for each VCG. According to the preferred embodiment, the read logic is provided in two parts separated by a temporary buffer. The first part of the read logic performs the functions described above and writes chunk data into the temporary buffer. The second part of the read logic reads byte data from the temporary buffer according to a selectable leak rate.
摘要翻译：写入逻辑和读取逻辑耦合到SDRAM和帧状态表。 VCG成员通过写逻辑写入SDRAM，帧状态表中的条目（基于MFI和SQ）由每个成员的写入逻辑维护。读逻辑扫描帧状态表以识别SDRAM中数据可用的最早帧号。基于帧状态和地址指针偏移，读逻辑维护每个VCG成员的状态表条目和每个VCG的状态。根据优选实施例，读逻辑被提供在由临时缓冲器分开的两个部分中。读逻辑的第一部分执行上述功能，并将块数据写入临时缓冲区。读取逻辑的第二部分根据可选择的泄漏率从临时缓冲器读取字节数据。

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