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1. 发明授权

US06823585B2 Method of selective plating on a substrate 失效
标题翻译：在基板上选择性镀覆的方法
公开(公告)号：US06823585B2
公开(公告)日：2004-11-30
申请号：US10249305
申请日：2003-03-28
申请人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
发明人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
IPC分类号： H01R4300
CPC分类号： H05K3/242 , H05K1/0306 , H05K3/0035 , H05K3/048 , H05K3/184 , H05K3/225 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49158 , Y10T29/49163 , Y10T29/49165 , Y10T29/49171 , Y10T29/49172 , Y10T29/49721 , Y10T29/49732 , Y10T29/49737 , Y10T29/49746
摘要： A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.
摘要翻译：在基板上形成表面电镀金属化的方法和结构。将两层胶带施加到基材的表面。通过暴露衬底表面的两层带切割第一路径。第一路径在衬底的顶表面上连接至少一个导电通孔。通过暴露第一层胶带的第二层胶带切割第二条路径。第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。去除胶带时，去除牺牲路径。

2. 发明授权

US07897059B2 High tin solder etching solution 有权
标题翻译：高锡锡蚀刻溶液
公开(公告)号：US07897059B2
公开(公告)日：2011-03-01
申请号：US11937646
申请日：2007-11-09
申请人： Richard F. Indyk , Krystyna W. Semkow
发明人： Richard F. Indyk , Krystyna W. Semkow
IPC分类号： C03C15/00
CPC分类号： C23G1/10 , B23K1/0016 , B23K3/0623 , B23K35/262 , B23K35/3601 , B23K2103/08 , C23F1/30 , C23F1/44 , H05K3/26 , H05K3/3478 , H05K2203/0113 , H05K2203/0338
摘要： A method is provided for the removal of tin or tin alloys from substrates such as the removal of residual tin solder from the molds used in the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and uses an etchant composition comprising cupric ions and HCl. Cupric chloride and cupric sulfate are preferred. A preferred method regenerates cupric ions by bubbling air or oxygen through the etchant solution during the cleaning process.
摘要翻译：提供了一种用于从基底去除锡或锡合金的方法，例如从用于制造晶片或其它电子器件上的互连焊料凸块的模具中除去残留的锡焊料。该方法对于众所周知的C4NP互连技术特别有用，并且使用包含铜离子和HCl的蚀刻剂组合物。氯化铜和硫酸铜是优选的。优选的方法是通过在清洁过程中通过蚀刻剂溶液鼓泡空气或氧气来再生铜离子。

3. 发明申请

US20090120999A1 HIGH TIN SOLDER ETCHING SOLUTION 有权
标题翻译：高锡焊蚀刻溶液
公开(公告)号：US20090120999A1
公开(公告)日：2009-05-14
申请号：US11937646
申请日：2007-11-09
申请人： Richard F. Indyk , Krystyna W. Semkow
发明人： Richard F. Indyk , Krystyna W. Semkow
IPC分类号： B23K31/02 , B08B3/04 , C09K13/04
CPC分类号： C23G1/10 , B23K1/0016 , B23K3/0623 , B23K35/262 , B23K35/3601 , B23K2103/08 , C23F1/30 , C23F1/44 , H05K3/26 , H05K3/3478 , H05K2203/0113 , H05K2203/0338
摘要： A method is provided for the removal of tin or tin alloys from substrates such as the removal of residual tin solder from the molds used in the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and uses an etchant composition comprising cupric ions and HCl. Cupric chloride and cupric sulfate are preferred. A preferred method regenerates cupric ions by bubbling air or oxygen through the etchant solution during the cleaning process.
摘要翻译：提供了一种用于从基底去除锡或锡合金的方法，例如从用于制造晶片或其它电子器件上的互连焊料凸块的模具中除去残留的锡焊料。该方法对于众所周知的C4NP互连技术特别有用，并且使用包含铜离子和HCl的蚀刻剂组合物。氯化铜和硫酸铜是优选的。优选的方法是通过在清洁过程中通过蚀刻剂溶液鼓泡空气或氧气来再生铜离子。

4. 发明授权

US06835260B2 Method to produce pedestal features in constrained sintered substrates 失效
公开(公告)号：US06835260B2
公开(公告)日：2004-12-28
申请号：US10265516
申请日：2002-10-04
申请人： Benjamin V. Fasano , David H. Gabriels , Richard F. Indyk , Glenn A. Pomerantz , Richard A. Shelleman
发明人： Benjamin V. Fasano , David H. Gabriels , Richard F. Indyk , Glenn A. Pomerantz , Richard A. Shelleman
IPC分类号： B32B3118
CPC分类号： B32B18/00 , B32B38/0004 , B32B2310/0843 , C04B2237/32 , C04B2237/341 , C04B2237/52 , C04B2237/56 , C04B2237/561 , C04B2237/562 , C04B2237/62 , C04B2237/68 , C04B2237/702 , H01L21/4807 , H01L21/481 , H05K1/0306 , H05K3/4611 , H05K3/4629 , H05K3/4697 , H05K2203/063 , H05K2203/308 , Y10T156/1082
摘要： Methods to create raised pedestal parts in ceramic substrates sintered under a load. The invention uses a patterned, buried, non-sintering layer that provides the needed transfer of load during the sintering process to the raised or pedestal portion of the substrate while maintaining dimensional control of the metallized features on the surface of the pedestal base. The methods involve cutting channels in the ceramic substrate corresponding in position to the perimeter of the opening in the patterned non-sintering contact sheet. The channels may be cut either before or after the sintering of the ceramic substrates.

5. 发明申请

US20080218971A1 METHOD AND STRUCTURE TO IMPROVE THERMAL DISSIPATION FROM SEMICONDUCTOR DEVICES 失效
公开(公告)号：US20080218971A1
公开(公告)日：2008-09-11
申请号：US11681994
申请日：2007-03-05
申请人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
发明人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
IPC分类号： H05K7/20
CPC分类号： H01L21/4871 , H01L21/50 , H01L23/3675 , H01L24/16 , H01L24/31 , H01L25/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/09701 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19105 , H01L2924/00 , H01L2224/0401
摘要： A method and structure of improving thermal dissipation from a module assembly include attaching a first side of at least one chip to a single chip carrier, the at least one chip having a second side opposite of the first side; grinding the second side of the at least one chip to a desired surface profile; applying a heat transfer medium on at least one of a heat sink and the second side of the at least one chip; and disposing the heat sink on the second side of the at least one chip with the heat transfer medium therebetween defining a gap between the heat sink and the second side of the at least one chip. The gap is controlled to improve heat transfer from the second side of the at least one chip to the heat sink.

6. 发明授权

US07468886B2 Method and structure to improve thermal dissipation from semiconductor devices 失效
标题翻译：改善半导体器件散热的方法和结构
公开(公告)号：US07468886B2
公开(公告)日：2008-12-23
申请号：US11681994
申请日：2007-03-05
申请人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
发明人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
IPC分类号： H05K7/20 , H01L21/48 , H01L23/10
CPC分类号： H01L21/4871 , H01L21/50 , H01L23/3675 , H01L24/16 , H01L24/31 , H01L25/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/09701 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19105 , H01L2924/00 , H01L2224/0401
摘要： A method and structure of improving thermal dissipation from a module assembly include attaching a first side of at least one chip to a single chip carrier, the at least one chip having a second side opposite of the first side; grinding the second side of the at least one chip to a desired surface profile; applying a heat transfer medium on at least one of a heat sink and the second side of the at least one chip; and disposing the heat sink on the second side of the at least one chip with the heat transfer medium therebetween defining a gap between the heat sink and the second side of the at least one chip. The gap is controlled to improve heat transfer from the second side of the at least one chip to the heat sink.
摘要翻译：改进模块组件散热的方法和结构包括将至少一个芯片的第一侧附接到单个芯片载体上，所述至少一个芯片具有与第一侧相对的第二侧; 将所述至少一个芯片的第二侧研磨成所需的表面轮廓; 在散热片和所述至少一个芯片的第二面中的至少一个上施加传热介质; 以及将所述散热器布置在所述至少一个芯片的第二侧上，其中所述传热介质在所述散热器和所述至少一个芯片的所述第二侧之间限定间隙。控制间隙以改善从至少一个芯片的第二侧到散热器的热传递。

7. 发明授权

US07724527B2 Method and structure to improve thermal dissipation from semiconductor devices 失效
标题翻译：改善半导体器件散热的方法和结构
公开(公告)号：US07724527B2
公开(公告)日：2010-05-25
申请号：US12197481
申请日：2008-08-25
申请人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
发明人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
IPC分类号： H05K7/20 , H01L21/56 , H01H23/10 , H01H21/48
CPC分类号： H01L21/4871 , H01L21/50 , H01L23/3675 , H01L24/16 , H01L24/31 , H01L25/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/09701 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19105 , H01L2924/00 , H01L2224/0401
摘要： A method and structure of improving thermal dissipation from a module assembly include attaching a first side of at least one chip to a single chip carrier, the at least one chip having a second side opposite of the first side; grinding the second side of the at least one chip to a desired surface profile; applying a heat transfer medium on at least one of a heat sink and the second side of the at least one chip; and disposing the heat sink on the second side of the at least one chip with the heat transfer medium therebetween defining a gap between the heat sink and the second side of the at least one chip. The gap is controlled to improve heat transfer from the second side of the at least one chip to the heat sink.
摘要翻译：改进模块组件散热的方法和结构包括将至少一个芯片的第一侧附接到单个芯片载体上，所述至少一个芯片具有与第一侧相对的第二侧; 将所述至少一个芯片的第二侧研磨成所需的表面轮廓; 在散热片和所述至少一个芯片的第二面中的至少一个上施加传热介质; 以及将所述散热器布置在所述至少一个芯片的第二侧上，其中所述传热介质在所述散热器和所述至少一个芯片的所述第二侧之间限定间隙。控制间隙以改善从至少一个芯片的第二侧到散热器的热传递。

8. 发明申请

US20080310117A1 METHOD AND STRUCTURE TO IMPROVE THERMAL DISSIPATION FROM SEMICONDUCTOR DEVICES 失效
标题翻译：从半导体器件中改进热释放的方法和结构
公开(公告)号：US20080310117A1
公开(公告)日：2008-12-18
申请号：US12197481
申请日：2008-08-25
申请人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
发明人： Patrick A. Coico , David L. Edwards , Richard F. Indyk , David C. Long
IPC分类号： H05K7/20
CPC分类号： H01L21/4871 , H01L21/50 , H01L23/3675 , H01L24/16 , H01L24/31 , H01L25/16 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/09701 , H01L2924/10158 , H01L2924/10253 , H01L2924/14 , H01L2924/15312 , H01L2924/16152 , H01L2924/19105 , H01L2924/00 , H01L2224/0401
摘要： A method and structure of improving thermal dissipation from a module assembly include attaching a first side of at least one chip to a single chip carrier, the at least one chip having a second side opposite of the first side; grinding the second side of the at least one chip to a desired surface profile; applying a heat transfer medium on at least one of a heat sink and the second side of the at least one chip; and disposing the heat sink on the second side of the at least one chip with the heat transfer medium therebetween defining a gap between the heat sink and the second side of the at least one chip. The gap is controlled to improve heat transfer from the second side of the at least one chip to the heat sink.
摘要翻译：改进模块组件散热的方法和结构包括将至少一个芯片的第一侧附接到单个芯片载体上，所述至少一个芯片具有与第一侧相对的第二侧; 将所述至少一个芯片的第二侧研磨成所需的表面轮廓; 在散热片和所述至少一个芯片的第二面中的至少一个上施加传热介质; 以及将所述散热器布置在所述至少一个芯片的第二侧上，其中所述传热介质在所述散热器和所述至少一个芯片的所述第二侧之间限定间隙。控制间隙以改善从至少一个芯片的第二侧到散热器的热传递。

9. 发明授权

US06261927B1 Method of forming defect-free ceramic structures using thermally depolymerizable surface layer 失效
标题翻译：使用可热解聚表面层形成无缺陷陶瓷结构的方法
公开(公告)号：US06261927B1
公开(公告)日：2001-07-17
申请号：US09302943
申请日：1999-04-30
申请人： Govindarajan Natarajan , Richard F. Indyk , Vincent P. Peterson , Krishna G. Sachdev
发明人： Govindarajan Natarajan , Richard F. Indyk , Vincent P. Peterson , Krishna G. Sachdev
IPC分类号： H01L2130
CPC分类号： H01L21/481 , H01L23/49894 , H01L2924/0002 , H01L2924/09701 , H01L2924/12044 , Y10S438/976 , H01L2924/00
摘要： This invention relates generally to a new method of forming semiconductor substrates with defect-free surface metallurgical features. In particular, the invention related to a method for providing surface protected ceramic green sheet laminates using at least one thermally depolymerizable surface layer. More particularly, the invention encompasses a method for fabricating semiconductor substrates wherein a thermally depolymerizable/decomposable surface film is placed over a ceramic green sheet stack or assembly prior to lamination and caused to conform to the surface topography of the green sheet during lamination. The invention also encompasses a method for fabricating surface protected green sheet laminates which can be sized or diced without causing process related defects on the ceramic surface. After lamination the thermally depolymerizable/decomposable film is conveniently and cleanly removed due to thermal depolymerization and burn-off of volatile species during the sintering process, thus providing surface defect-free ceramic substrates.
摘要翻译：本发明一般涉及一种形成具有无缺陷表面冶金特征的半导体衬底的新方法。特别地，本发明涉及使用至少一个可热解聚表面层来提供表面保护的陶瓷生片层叠体的方法。更具体地说，本发明包括一种制造半导体衬底的方法，其中在层压之前将热可解聚/可分解的表面薄膜放置在陶瓷生片层或组件上方并使其在叠层过程中符合生片的表面形貌。本发明还包括用于制造表面保护的生片层压板的方法，其可以在陶瓷表面上不引起工艺相关缺陷的尺寸或切割。在层压之后，由于在烧结过程中挥发物质的热解聚和燃烧，因此可方便且清洁地除去热可分解/可分解的膜，从而提供无表面缺陷的陶瓷基材。

10. 发明授权

US08652941B2 Wafer dicing employing edge region underfill removal 有权
标题翻译：晶圆切割采用边缘区域底部填充去除
公开(公告)号：US08652941B2
公开(公告)日：2014-02-18
申请号：US13474090
申请日：2012-05-17
申请人： Richard F. Indyk , Jae-Woong Nah , Satoru Katsurayama , Daisuke Oka , Shigefumi Okada
发明人： Richard F. Indyk , Jae-Woong Nah , Satoru Katsurayama , Daisuke Oka , Shigefumi Okada
IPC分类号： H01L21/78 , H01L21/46 , H01L21/301 , H01L21/44 , H01L21/50
CPC分类号： H01L24/27 , H01L21/78 , H01L24/29 , H01L2224/2732 , H01L2224/27416 , H01L2224/27418 , H01L2224/278 , H01L2224/27831 , H01L2224/2784 , H01L2224/2919 , H01L2224/94 , H01L2924/12042 , H01L2924/00014 , H01L2924/0665 , H01L2224/27 , H01L2924/00
摘要： In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery can be employed to align a blade to dice the chip-containing substrate. In another embodiment, an underfill layer is formed prior to any laser grooving. Mechanical cutting of the underfill layer from above dicing channels is followed by laser ablation of the dicing channels and subsequent mechanical cutting to dice a chip-containing substrate.
摘要翻译：在一个实施例中，通过在含芯片的衬底的切割通道上进行的激光切槽，将含有金属结构的电介质材料层从含芯片的衬底烧蚀。随后，以不包括含芯片的衬底的周边区域的图案在电介质材料层上形成底部填充层。可以使用在周边处的物理暴露的切割通道来对齐刀片以将含芯片的基底切割。在另一个实施例中，在任何激光切槽之前形成底部填充层。从切割通道上方对底部填充层进行机械切割，随后切割通道的激光烧蚀和随后的机械切割以切割含芯片的基底。

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