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    • 2. 发明授权
    • Integrated tip strain sensor for use in combination with a single axis
atomic force microscope
    • 集成尖端应变传感器,与单轴原子力显微镜组合使用
    • US5345816A
    • 1994-09-13
    • US157800
    • 1993-11-24
    • Joachim ClabesHenri A. KhouryLaszlo Landstein
    • Joachim ClabesHenri A. KhouryLaszlo Landstein
    • G01B21/30G01B7/34G01N27/00G01N37/00G01Q20/04G01Q60/24G01Q60/38G01Q60/42G03F7/20G01N23/00
    • G01Q60/38B82Y35/00G01B7/012G01Q20/04G03F7/70633Y10S977/852Y10S977/878
    • An integrated tip strain sensor is combination with a single axis atomic force microscope (AFM) for determining the profile of a surface in three dimensions. A cantilever beam carries an integrated tip stem on which is deposited a piezoelectric film strain sensor. A high-resolution direct electron beam (e-beam) deposition process is used to grow a sharp tip onto the silicon (Si) cantilever structure. The direct e-beam deposition process permits the controllable fabrication of high-aspect ratio, nanometer-scale tip structures. A piezoelectric jacket with four superimposed elements is deposited on the tip stem. The piezoelectric sensors function in a plane perpendicular to that of a probe in the AFM; that is, any tip contact with the linewidth surface will cause tip deflection with a corresponding proportional electrical signal output. This tip strain sensor, coupled to a standard single axis AFM tip, allows for three-dimensional metrology with a much simpler approach while avoiding catastrophic tip "crashes". Two-dimensional edge detection of the sidewalls is used to calculate the absolute value or the linewidth of overlay, independent of the AFM principle. The technique works on any linewidth surface material, whether conductive, non-conductive or semiconductive.
    • 集成尖端应变传感器与单轴原子力显微镜(AFM)组合,用于确定三维表面的轮廓。 悬臂梁载有集成的尖端杆,其上沉积有压电薄膜应变传感器。 使用高分辨率直接电子束(电子束)沉积工艺将锋利的尖端生长到硅(Si)悬臂结构上。 直接电子束沉积工艺允许可控制造高纵横比,纳米尺度的尖端结构。 具有四个叠加元件的压电护套沉积在尖端杆上。 压电传感器在与AFM中的探头垂直的平面中起作用; 也就是说,与线宽表面的任何尖端接触将导致尖端偏转与相应的比例电信号输出。 这种尖端应变传感器与标准的单轴AFM尖端相连,允许采用更简单的方法进行三维计量,同时避免灾难性的尖端“崩溃”。 使用侧壁的二维边缘检测来计算覆盖层的绝对值或线宽,而与AFM原理无关。 该技术适用于任何线宽表面材料,无论是导电,非导电或半导体。
    • 4. 发明授权
    • Chip registration mechanism
    • 芯片注册机制
    • US4600936A
    • 1986-07-15
    • US513188
    • 1983-07-12
    • Henri A. KhouryBruce E. Tompkins
    • Henri A. KhouryBruce E. Tompkins
    • H01L21/68B65D85/57B65D85/86G05D3/00H01L21/67H01L21/673H01L21/677H01L23/42H01L23/44H01L23/46
    • H01L21/67333H01L21/67787H01L2221/68313Y10T29/41
    • A chip registration mechanism may form a part of a carrier for retaining in position a plurality of integrated circuit chips in row and column fashion having identification codes on one surface thereof, such that the chip codes may be read and cooperate with a tray having multiple cells, with each cell receiving an individual integrated circuit chip, or function to position a single chip relative to a reference surface for processing. A chip registration base member includes a pedestal projecting upwardly from a base member within a cavity having transverse dimensions oversized relative to the chip and defining at least one lateral reference surface. A lid extends across the top of the member partially defines the cavity above the chip with the chip resting on the top of the pedestal. Inclined nozzles carried by the pedestal function to jet air from the pedestal top surface against the bottom of the chip to create an air film to support the chip and to impart a force laterally to move the edge of the chip against the cavity reference surface. A relief channel about the base of the pedestal open to the atmosphere prevents flutter of the chip and insures accurate registration contact of the edge of the chip against the cavity reference surface. The same nozzle carried by the pedestal function to vacuum the bottom of the chip against the pedestal top surface to clamp the chip in this orientation.
    • 芯片配准机构可以形成载体的一部分,用于在其表面上具有标识码的行和列方式保持多个集成电路芯片的位置,使得可以读取芯片代码并与具有多个单元的托盘配合 每个单元接收单独的集成电路芯片,或者用于相对于参考表面定位单个芯片以用于处理的功能。 芯片对准基座构件包括从腔体内的基部构件向上突出的底座,其具有相对于芯片尺寸过大并且限定至少一个横向参考表面的横向尺寸。 盖子延伸穿过构件的顶部部分地限定芯片上方的空腔,其中芯片搁置在基座的顶部上。 由基座功能承载的倾斜喷嘴将基座顶表面的空气喷射到芯片的底部以产生空气膜以支撑芯片并且横向地施加力以将芯片的边缘移动抵靠空腔参考表面。 围绕基座的底座的大致开放通道防止芯片颤动并确保芯片的边缘与空腔参考表面的准确对准接触。 由基座功能承载的相同的喷嘴将芯片的底部压靠在基座顶部表面上,以将芯片夹紧在该取向中。
    • 7. 发明授权
    • Optical emission spectroscopy end point detection in plasma etching
    • 等离子体蚀刻中的光发射光谱终点检测
    • US4493745A
    • 1985-01-15
    • US575611
    • 1984-01-31
    • Lee ChenHenri A. KhouryHarlan R. Seymour
    • Lee ChenHenri A. KhouryHarlan R. Seymour
    • H01L21/302C23F4/00H01J37/32H01L21/3065B44C1/22C03C15/00C03C25/06
    • H01J37/32935C23F4/00
    • A method for etching a batch of semiconductor wafers to end point using optical emission spectroscopy is described. The method is applicable to any form of dry plasma etching which produces an emission species capable of being monitored. In a preferred embodiment, as well as a first alternative embodiment, a computer simulation is performed using an algorithm describing the concentration of the monitored etch species within the etching chamber as a function of time. The simulation produces a time period for continuing the etching process past a detected time while monitoring the intensity of emission of the etch species. In a second alternative embodiment, this latter time period is calculated using mathematical distributions describing the parameters of the etching process. In all three embodiments, the actual time that end point of an etching process is reached is closely approximated. In this manner, all wafers in a batch of wafers being etched reach end point while at the same time, the amount of over etching is greatly minimized.
    • 描述了使用光发射光谱法将一批半导体晶片蚀刻到终点的方法。 该方法适用于产生能够被监测的发射物质的任何形式的干等离子体蚀刻。 在优选实施例中,以及第一替代实施例,使用描述作为时间的函数的蚀刻室内监测的蚀刻物质的浓度的算法来执行计算机模拟。 模拟产生一个时间段,用于在监测蚀刻物质的发射强度的同时,在检测到的时间内继续蚀刻工艺。 在第二替代实施例中,使用描述蚀刻工艺的参数的数学分布来计算后一时间段。 在所有三个实施例中,达到蚀刻工艺的终点的实际时间是非常接近的。 以这种方式,一批待蚀刻的晶片中的所有晶片都到达终点,而同时过度蚀刻的量大大减至最小。