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1. 发明授权

US06420236B1 Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices 有权
标题翻译：金属栅极MOSFET器件阈值电压漂移的氢处理
公开(公告)号：US06420236B1
公开(公告)日：2002-07-16
申请号：US09641053
申请日：2000-08-17
申请人： Jerry C. Hu , Hong Yang , Amitava Chatterjee , Ih-Chin Chen
发明人： Jerry C. Hu , Hong Yang , Amitava Chatterjee , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L21/324 , H01L21/28176 , H01L29/4966 , H01L29/66545
摘要： A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming 200 a gate oxide layer on a semiconductor substrate, forming 210 a dummy gate on the substrate, removing 260 the dummy gate after further processing and depositing 270 a lower metallic gate material on said gate oxide; treating 280 the semiconductor device with a reducing gas immediately after deposition of the lower metallic gate material, and depositing 290 an upper gate metal over the lower gate material.
摘要翻译：公开了一种用于制造具有相对低的阈值电压的金属栅极MOSFET的系统，包括以下步骤：在半导体衬底上形成200个栅极氧化物层，在衬底上形成一个虚拟栅极，在进一步处理之后移除260个虚拟栅极并沉积270个所述栅极氧化物上的下部金属栅极材料; 在沉积下部金属栅极材料之后立即用还原气体处理280半导体器件，并在上部栅极材料上沉积290个上部栅极金属。

2. 发明授权

US06228725B1 Semiconductor devices with pocket implant and counter doping 有权
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US06228725B1
公开(公告)日：2001-05-08
申请号：US09281543
申请日：1999-03-30
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

3. 发明授权

US06313010B1 Integrated circuit insulator and method 失效
标题翻译：集成电路绝缘子及方法
公开(公告)号：US06313010B1
公开(公告)日：2001-11-06
申请号：US08871738
申请日：1997-06-09
申请人： Somnath S. Nag , Amitava Chatterjee , Ih-Chin Chen
发明人： Somnath S. Nag , Amitava Chatterjee , Ih-Chin Chen
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , Y10S148/05
摘要： A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (122) with chemical mechanical polishing removal of non-trench oxide.
摘要翻译：一种沟槽隔离结构，包括高密度等离子体加强二氧化硅沟槽填充（122），化学机械抛光去除非沟槽氧化物。

4. 发明授权

US5917219A Semiconductor devices with pocket implant and counter doping 失效
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US5917219A
公开(公告)日：1999-06-29
申请号：US725599
申请日：1996-10-03
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L27/01 , H01L27/12 , H01L31/0397
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

5. 发明授权

US5548548A Pass transistor for a 256 megabit dram with negatively biased substrate 失效
标题翻译：传输晶体管为256兆字节与负偏置的基板
公开(公告)号：US5548548A
公开(公告)日：1996-08-20
申请号：US358647
申请日：1994-12-19
申请人： Amitava Chatterjee , Jiann Liu , Purnendu Mozumder , Mark S. Rodder , Ih-Chin Chen
发明人： Amitava Chatterjee , Jiann Liu , Purnendu Mozumder , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L29/78 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/10 , H01L29/423 , G11C11/401
CPC分类号： H01L27/10873 , G11C11/404 , H01L29/1087 , H01L29/42364 , H01L29/42376
摘要： A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.
摘要翻译：实现256 Mbit DRAM器件的传输晶体管的设计。栅极长度约为0.3μm的晶体管，约为85安培的毒素，其比0.25微米逻辑技术的DIFFERENCE 65 ANGSTROM毒is厚，V VL为3.75伏，Vsub为-1伏，砷 LDD和沟道区域中的硼浓度约为2.7x1017 / cm3，是256 Mbit DRAM器件的理想选择。

6. 发明授权

US6143625A Protective liner for isolation trench side walls and method 有权
标题翻译：隔离沟侧墙保护衬垫及方法
公开(公告)号：US6143625A
公开(公告)日：2000-11-07
申请号：US151374
申请日：1998-09-10
申请人： Ih-Chin Chen , Amitava Chatterjee , Somnath S. Nag
发明人： Ih-Chin Chen , Amitava Chatterjee , Somnath S. Nag
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).
摘要翻译：隔离沟槽（60）可以包括形成在半导体层（12）中的沟槽（20）。阻挡层（22）可以沿着沟槽（20）形成。可以在阻挡层（22）上方形成保护衬垫（50）。保护性衬垫（50）可以包括化学沉积的氧化物。绝缘材料（55）的高密度层可以形成在保护衬垫（50）上的沟槽（20）中。

7. 发明授权

US5909628A Reducing non-uniformity in a refill layer thickness for a semiconductor device 失效
标题翻译：降低半导体器件的再填充层厚度的不均匀性
公开(公告)号：US5909628A
公开(公告)日：1999-06-01
申请号：US804484
申请日：1997-02-21
申请人： Amitava Chatterjee , Theodore W. Houston , Ih-Chin Chen , Agerico L. Esquirel , Somnath Nag , Iqbal Ali , Keith A. Joyner , Yin Hu , Jeffrey Alan McKee , Peter Stewart McAnally
发明人： Amitava Chatterjee , Theodore W. Houston , Ih-Chin Chen , Agerico L. Esquirel , Somnath Nag , Iqbal Ali , Keith A. Joyner , Yin Hu , Jeffrey Alan McKee , Peter Stewart McAnally
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3105 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.
摘要翻译：制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。

8. 发明申请

US20120275207A1 SRAM CELL PARAMETER OPTIMIZATION 有权
标题翻译： SRAM单元参数优化
公开(公告)号：US20120275207A1
公开(公告)日：2012-11-01
申请号：US13097370
申请日：2011-04-29
申请人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
发明人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
IPC分类号： G11C11/412 , H01L21/8244
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.
摘要翻译：具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。另外，提供了具有SRAM单元的集成电路的制造方法。

9. 发明授权

US08053322B2 Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom 有权
标题翻译：用于减小沟槽边缘处栅极电介质薄化的外延沉积工艺及其集成电路
公开(公告)号：US08053322B2
公开(公告)日：2011-11-08
申请号：US12344995
申请日：2008-12-29
申请人： Vladimir F. Drobny , Amitava Chatterjee , Phillipp Steinmann , Rick Wise
发明人： Vladimir F. Drobny , Amitava Chatterjee , Phillipp Steinmann , Rick Wise
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/76229 , H01L21/823481 , H01L21/823878 , H01L29/1087 , H01L29/66651
摘要： A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed.
摘要翻译：一种制造集成电路（IC）及其IC的方法，包括多个金属氧化物半导体（MOS）晶体管，其栅极电介质薄膜在沟槽隔离/半导体边缘处具有减小的栅极电介质薄化和拐角锐化，用于通常为500至5000埃厚的栅极电介质层。该方法包括提供具有包含硅的表面的衬底。在衬底中形成多个电介质填充沟槽隔离区。包括表面的硅在其周边与沟槽隔离区形成沟槽隔离有源区边缘。沉积外延硅层，其中包含硅层的外延形成在包含硅的表面上。包含硅层的外延被氧化以将至少一部分转化成热生长的氧化硅层，其中热生长的氧化硅层为所述多个MOS晶体管中的至少一个提供至少一部分栅极电介质层。在栅极电介质上形成图案化的栅极电极层，其中图案化的栅极电极层在沟槽隔离有源区域边缘中的至少一个上延伸。然后完成IC的制造。

10. 发明申请

US20100274506A1 METHOD FOR MEASURING INTERFACE TRAPS IN THIN GATE OXIDE MOSFETS 有权
标题翻译：用于测量薄壁氧化物MOSFET中的界面行为的方法
公开(公告)号：US20100274506A1
公开(公告)日：2010-10-28
申请号：US12831122
申请日：2010-07-06
申请人： Tathagata Chatterjee , Amitava Chatterjee
发明人： Tathagata Chatterjee , Amitava Chatterjee
IPC分类号： G01R31/26 , G06F19/00
CPC分类号： G01R31/2621
摘要： A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.
摘要翻译：一种用于测量MOSFET中的接口陷阱的方法，包括测量在预定频率范围内各种频率的脉冲波形的电荷泵浦电流，产生所测量的电荷泵浦电流相对于预定频率范围的绘制点，确定接口总数通过计算通过绘制点的最佳拟合线的斜率参与电荷泵浦电流的陷阱。

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