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1. 发明授权

US09059032B2 SRAM cell parameter optimization 有权
标题翻译： SRAM单元参数优化
公开(公告)号：US09059032B2
公开(公告)日：2015-06-16
申请号：US13097370
申请日：2011-04-29
申请人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
发明人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
IPC分类号： G11C11/00 , H01L27/11 , H01L27/02 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.
摘要翻译：具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。另外，提供了具有SRAM单元的集成电路的制造方法。

2. 发明申请

US20120275207A1 SRAM CELL PARAMETER OPTIMIZATION 有权
标题翻译： SRAM单元参数优化
公开(公告)号：US20120275207A1
公开(公告)日：2012-11-01
申请号：US13097370
申请日：2011-04-29
申请人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
发明人： Theodore W. Houston , Puneet Kohli , Amitava Chatterjee
IPC分类号： G11C11/412 , H01L21/8244
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.
摘要翻译：具有SRAM单元的集成电路包括一对交叉耦合的反相器，其中第一驱动器和负载晶体管被连接以提供第一存储节点和第二驱动器以及连接到第二存储节点的负载晶体管。 SRAM单元还包括由至少一个字线控制并分别连接在第一位线和第一存储节点之间的第一和第二通过栅极晶体管以及第二位线和第二存储节点; 其中第一驱动晶体管阈值电压不同于第二驱动晶体管阈值电压，并且第一和第二驱动器阈值电压中的一个不同于通过栅极晶体管阈值电压。或者，第一和第二驱动晶体管的阈值电压不同于对称的通过栅极晶体管阈值电压。另外，提供了具有SRAM单元的集成电路的制造方法。

3. 发明授权

US07897496B2 Semiconductor doping with reduced gate edge diode leakage 有权
标题翻译：半导体掺杂减少了栅极边缘二极管泄漏
公开(公告)号：US07897496B2
公开(公告)日：2011-03-01
申请号：US11941129
申请日：2007-11-16
申请人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
发明人： Puneet Kohli , Nandakumar Mahalingam , Manoj Mehrotra , Song Zhao
IPC分类号： H01L21/425
CPC分类号： H01L21/26513 , H01L21/26506 , H01L29/165 , H01L29/6659 , H01L29/7833
摘要： Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.
摘要翻译：公开了半导体掺杂技术以及相关方法和结构，其产生具有更紧密控制的源极和漏极延伸区掺杂物分布而不显着引起栅极边缘二极管泄漏的元件。该技术遵循发现，可以用作掺杂剂如硼的扩散抑制剂的碳可能在源极和漏极延伸区域中以大量存在而产生栅极边缘二极管泄漏。作为在源极和漏极延伸区域中放置碳的替代方案，可以将碳放置在源极和漏极区域中，并且可以依靠用于激活掺杂剂的热退火将碳的少量浓度扩散到源中，漏极延伸区域，从而抑制这些区域中的掺杂剂扩散，而不会显着引起栅极边缘二极管泄漏。源极和漏极区域中增加的碳浓度可能允许源极/漏极区域的较重掺杂，导致改善的栅极电容。

4. 发明授权

US07465635B2 Method for manufacturing a gate sidewall spacer using an energy beam treatment 有权
标题翻译：使用能量束处理制造栅极侧壁间隔物的方法
公开(公告)号：US07465635B2
公开(公告)日：2008-12-16
申请号：US11533798
申请日：2006-09-21
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823864 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其他步骤之外，用于制造半导体器件的方法可以包括在衬底上形成栅极结构，形成靠近栅极结构的侧壁的栅极侧壁间隔的至少一部分，以及使栅极侧壁间隔物的至少一部分能量束处理被配置为改变栅极侧壁间隔物的至少一部分的应力，从而改变其下的衬底中的应力。

5. 发明申请

US20060183302A1 Highly conductive shallow junction formation 有权
标题翻译：高导电性浅结结形成
公开(公告)号：US20060183302A1
公开(公告)日：2006-08-17
申请号：US11057509
申请日：2005-02-14
申请人： Puneet Kohli
发明人： Puneet Kohli
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/324 , H01L21/823814 , H01L29/6653 , H01L29/6659
摘要： The invention relates to a method of forming a shallow junction. The method (100) comprises forming source/drain extension regions with a non-amorphizing tail implant (105) which is annealed conventionally (spike/RTP) and amorphizing implant which is re-grown epitaxially (SPER) (110). The non-amorphizing tail implant is generally annealed (106) before a doped amorphous layer for SPE is formed (107). SPE provides a high active dopant concentration in a shallow layer. The non-amorphizing tail implant (105) expands the source/drain extension region beyond the range dictated by the SPE-formed layer and keeps the depletion region of the P-N junction away from where end-of-range defects form during the SPE process. Thus, the SPE-formed layer primarily determines the conductivity of the junction while the tail implant determines the location of the depletion region. End-of-range defects form, but are not in a position to cause significant reverse bias leakage.
摘要翻译：本发明涉及一种形成浅结的方法。方法（100）包括用非常失活的尾部植入物（105）形成源极/漏极延伸区域，其常规地退火（尖峰/ RTP）和再生长外延（SPER）的非晶化植入物（110）。在形成用于SPE的掺杂非晶层（107）之前，非非晶化尾部植入物通常退火（106）。 SPE在浅层中提供高活性掺杂剂浓度。非非晶化尾部植入物（105）将源极/漏极扩展区域扩展超过由SPE形成的层指定的范围，并且使得P-N结的耗尽区域远离在SPE工艺期间形成端部范围缺陷的位置。因此，SPE形成层主要确定结的导电性，而尾部植入物确定耗尽区的位置。端到端缺陷形成，但不能产生显着的反向偏置泄漏。

6. 发明申请

US20060105518A1 Ultra-shallow arsenic junction formation in silicon germanium 有权
标题翻译：硅锗中的超浅砷结点形成
公开(公告)号：US20060105518A1
公开(公告)日：2006-05-18
申请号：US11267413
申请日：2005-11-04
申请人： Puneet Kohli , Mark Rodder , Rick Wise , Amitabh Jain
发明人： Puneet Kohli , Mark Rodder , Rick Wise , Amitabh Jain
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/823807 , H01L21/823814 , H01L29/1054 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： In one aspect, the present invention provides a method of forming junctions in a silicon-germanium layer (20). In this particular embodiment, the method comprises implanting a dopant (80) into the silicon-germanium layer (20) and implanting fluorine (70) into the silicon-germanium layer (20).
摘要翻译：一方面，本发明提供一种在硅 - 锗层（20）中形成结的方法。在该特定实施例中，该方法包括将掺杂剂（80）注入到硅 - 锗层（20）中并将氟（70）注入到硅 - 锗层（20）中。

7. 发明授权

US08217426B2 Bipolar transistors with resistors 有权
标题翻译：带电阻的双极晶体管
公开(公告)号：US08217426B2
公开(公告)日：2012-07-10
申请号：US12731667
申请日：2010-03-25
申请人： Puneet Kohli
发明人： Puneet Kohli
IPC分类号： H01L21/8238
CPC分类号： H01L21/8249 , H01L27/0635 , Y10S148/009
摘要： Complementary MOS (CMOS) integrated circuits include MOS transistors, resistors and bipolar transistors formed on a common substrate. An emitter region of a bipolar transistor is implanted with a first dopant in an implantation process that implants source/drain regions of an MOS transistor, and is also implanted with a second dopant of same conductivity type in another implantation process that implants a body region of a resistor. The first and second dopants may optionally be the same dopant. The source/drain regions are implanted with the resistor body region covered by a first patterned mask; and the resistor body region is implanted with the MOS transistor source/drain regions covered by a second patterned mask. The implantations of the MOS transistor source/drain regions and of the resistor body region the source/drain regions can occur in any order, with the emitter region implanted during both implantations.
摘要翻译：互补MOS（CMOS）集成电路包括形成在公共衬底上的MOS晶体管，电阻器和双极晶体管。在注入MOS晶体管的源极/漏极区域的注入工艺中注入双极晶体管的发射极区域，并且在另一种注入工艺中注入相同导电类型的第二掺杂剂的植入工艺中，注入第一掺杂剂，一个电阻第一和第二掺杂剂可以任选地是相同的掺杂剂。源极/漏极区域注入由第一图案化掩模覆盖的电阻器体区域; 并且用第二图案掩模覆盖的MOS晶体管源极/漏极区域注入电阻体区域。源极/漏极区域的MOS晶体管源极/漏极区域和电阻器体区域的注入可以以任何顺序发生，在两个注入期间都注入发射极区域。

8. 发明申请

US20090179280A1 HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDUCE DAMAGE 有权
标题翻译：具有As，P和C的高阈值NMOS源 - 漏极形成以减少损害
公开(公告)号：US20090179280A1
公开(公告)日：2009-07-16
申请号：US11972417
申请日：2008-01-10
申请人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
发明人： Puneet Kohli , Manoj Mehrotra , Shaoping Tang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26586 , H01L21/823418 , H01L29/0847 , H01L29/6659 , H01L29/7833
摘要： Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implanatation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm−2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed
摘要翻译： n型轻掺杂漏极（NLDD）区域和n型源极/漏极（NDS）区域的管道缺陷与砷植入相关，而NLDD和NSD区域的过度扩散主要是由于磷间质运动。碳植入通常用于减少NLDD中的磷扩散，但有助于门极二极管泄漏（GDL）。在高阈值NMOS晶体管中，GDL通常是主要的截止状态泄漏机制。本发明提供了一种形成NMOS晶体管的方法，其中没有碳注入到NLDD中，并且NSD由前非晶化植入物（PAI），磷植入物和碳种植入物形成。在NDS中使用碳可以提供更高浓度的磷，从而降低串联电阻并减少管道缺陷。还公开了在NSD中具有小于1.1014cm-2砷的NMOS晶体管和由本发明方法形成的高阈值NMOS晶体管

9. 发明申请

US20080277730A1 Semiconductor Device Manufactured Using a Laminated Stress Layer 有权
标题翻译：使用层压应力层制造的半导体器件
公开(公告)号：US20080277730A1
公开(公告)日：2008-11-13
申请号：US11745044
申请日：2007-05-07
申请人： Manoj Mehrotra , Antonio L.P Rotondaro , Puneet Kohli
发明人： Manoj Mehrotra , Antonio L.P Rotondaro , Puneet Kohli
IPC分类号： H01L21/44 , H01L29/76
CPC分类号： H01L21/76832 , H01L21/76825 , H01L21/76828 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.
摘要翻译：提出了形成半导体器件的方法。该方法包括形成栅极结构，包括在半导体衬底上形成栅电极并在栅电极附近形成间隔物。在栅极结构附近形成源极/漏极，并且在栅极结构和半导体衬底上形成层压应力层。层压应力层的形成包括循环沉积工艺以在栅极结构和半导体衬底之上形成第一应力层，并且在第一应力层上形成至少第二应力层。在层压层形成之后，进行在约900℃以上的温度下进行的退火处理。

10. 发明申请

US20080076227A1 METHOD FOR FORMING A PRE-METAL DIELECTRIC LAYER USING AN ENERGY BEAM TREATMENT 审中-公开
标题翻译：使用能量束处理形成预金属介电层的方法
公开(公告)号：US20080076227A1
公开(公告)日：2008-03-27
申请号：US11533795
申请日：2006-09-21
申请人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
发明人： Puneet Kohli , Manoj Mehrotra , Jin Zhao , Sameer Ajmera
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/2686 , H01L21/76224 , H01L21/76825 , H01L29/6659 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes, among other steps, forming a gate structure over a substrate, the gate structure having source/drain regions proximate thereto and in, on or over the substrate, forming a pre-metal dielectric layer over the gate structure and source/drain regions, and subjecting the pre-metal dielectric layer to an energy beam treatment, the energy beam treatment configured to change a stress of the pre-metal dielectric layer, and thus change a stress in the substrate therebelow.
摘要翻译：本发明提供一种制造半导体器件的方法。除了其他步骤之外，用于制造半导体器件的方法包括在衬底上形成栅极结构，栅极结构具有靠近其的源极/漏极区域，并且在衬底上，衬底上或上方，在栅极上形成预金属电介质层结构和源极/漏极区域，并且对金属前介电层进行能量束处理，所述能量束处理被配置为改变预金属介电层的应力，从而改变其下的衬底中的应力。

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