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1. 发明授权

US6143625A Protective liner for isolation trench side walls and method 有权
标题翻译：隔离沟侧墙保护衬垫及方法
公开(公告)号：US6143625A
公开(公告)日：2000-11-07
申请号：US151374
申请日：1998-09-10
申请人： Ih-Chin Chen , Amitava Chatterjee , Somnath S. Nag
发明人： Ih-Chin Chen , Amitava Chatterjee , Somnath S. Nag
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S148/05
摘要： An isolation trench (60) may comprise a trench (20) formed in a semiconductor layer (12). A barrier layer (22) may be formed along the trench (20). A protective liner (50) may be formed over the barrier layer (22). The protective liner (50) may comprise a chemically deposited oxide. A high density layer of insulation material (55) may be formed in the trench (20) over the protective liner (50).
摘要翻译：隔离沟槽（60）可以包括形成在半导体层（12）中的沟槽（20）。阻挡层（22）可以沿着沟槽（20）形成。可以在阻挡层（22）上方形成保护衬垫（50）。保护性衬垫（50）可以包括化学沉积的氧化物。绝缘材料（55）的高密度层可以形成在保护衬垫（50）上的沟槽（20）中。

2. 发明授权

US06313010B1 Integrated circuit insulator and method 失效
标题翻译：集成电路绝缘子及方法
公开(公告)号：US06313010B1
公开(公告)日：2001-11-06
申请号：US08871738
申请日：1997-06-09
申请人： Somnath S. Nag , Amitava Chatterjee , Ih-Chin Chen
发明人： Somnath S. Nag , Amitava Chatterjee , Ih-Chin Chen
IPC分类号： H01L2176
CPC分类号： H01L21/76229 , H01L21/76224 , Y10S148/05
摘要： A trench isolation structure including high density plasma enchanced silicon dioxide trench filling (122) with chemical mechanical polishing removal of non-trench oxide.
摘要翻译：一种沟槽隔离结构，包括高密度等离子体加强二氧化硅沟槽填充（122），化学机械抛光去除非沟槽氧化物。

3. 发明授权

US06228725B1 Semiconductor devices with pocket implant and counter doping 有权
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US06228725B1
公开(公告)日：2001-05-08
申请号：US09281543
申请日：1999-03-30
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

4. 发明授权

US06420236B1 Hydrogen treatment for threshold voltage shift of metal gate MOSFET devices 有权
标题翻译：金属栅极MOSFET器件阈值电压漂移的氢处理
公开(公告)号：US06420236B1
公开(公告)日：2002-07-16
申请号：US09641053
申请日：2000-08-17
申请人： Jerry C. Hu , Hong Yang , Amitava Chatterjee , Ih-Chin Chen
发明人： Jerry C. Hu , Hong Yang , Amitava Chatterjee , Ih-Chin Chen
IPC分类号： H01L21336
CPC分类号： H01L21/324 , H01L21/28176 , H01L29/4966 , H01L29/66545
摘要： A system for producing metal gate MOSFETs having relatively low threshold voltages is disclosed, comprising the steps of forming 200 a gate oxide layer on a semiconductor substrate, forming 210 a dummy gate on the substrate, removing 260 the dummy gate after further processing and depositing 270 a lower metallic gate material on said gate oxide; treating 280 the semiconductor device with a reducing gas immediately after deposition of the lower metallic gate material, and depositing 290 an upper gate metal over the lower gate material.
摘要翻译：公开了一种用于制造具有相对低的阈值电压的金属栅极MOSFET的系统，包括以下步骤：在半导体衬底上形成200个栅极氧化物层，在衬底上形成一个虚拟栅极，在进一步处理之后移除260个虚拟栅极并沉积270个所述栅极氧化物上的下部金属栅极材料; 在沉积下部金属栅极材料之后立即用还原气体处理280半导体器件，并在上部栅极材料上沉积290个上部栅极金属。

5. 发明授权

US5917219A Semiconductor devices with pocket implant and counter doping 失效
标题翻译：具有袋式注入和反掺杂的半导体器件
公开(公告)号：US5917219A
公开(公告)日：1999-06-29
申请号：US725599
申请日：1996-10-03
申请人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
发明人： Mahalingam Nandakumar , Amitava Chatterjee , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L21/336 , H01L29/10 , H01L29/78 , H01L27/01 , H01L27/12 , H01L31/0397
CPC分类号： H01L29/66575 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/7838
摘要： A low power transistor (70, 70') formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80') of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82', 84') of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80').
摘要翻译：形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

6. 发明授权

US5548548A Pass transistor for a 256 megabit dram with negatively biased substrate 失效
标题翻译：传输晶体管为256兆字节与负偏置的基板
公开(公告)号：US5548548A
公开(公告)日：1996-08-20
申请号：US358647
申请日：1994-12-19
申请人： Amitava Chatterjee , Jiann Liu , Purnendu Mozumder , Mark S. Rodder , Ih-Chin Chen
发明人： Amitava Chatterjee , Jiann Liu , Purnendu Mozumder , Mark S. Rodder , Ih-Chin Chen
IPC分类号： H01L29/78 , G11C11/404 , H01L21/8242 , H01L27/108 , H01L29/10 , H01L29/423 , G11C11/401
CPC分类号： H01L27/10873 , G11C11/404 , H01L29/1087 , H01L29/42364 , H01L29/42376
摘要： A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.
摘要翻译：实现256 Mbit DRAM器件的传输晶体管的设计。栅极长度约为0.3μm的晶体管，约为85安培的毒素，其比0.25微米逻辑技术的DIFFERENCE 65 ANGSTROM毒is厚，V VL为3.75伏，Vsub为-1伏，砷 LDD和沟道区域中的硼浓度约为2.7x1017 / cm3，是256 Mbit DRAM器件的理想选择。

7. 发明授权

US5909628A Reducing non-uniformity in a refill layer thickness for a semiconductor device 失效
标题翻译：降低半导体器件的再填充层厚度的不均匀性
公开(公告)号：US5909628A
公开(公告)日：1999-06-01
申请号：US804484
申请日：1997-02-21
申请人： Amitava Chatterjee , Theodore W. Houston , Ih-Chin Chen , Agerico L. Esquirel , Somnath Nag , Iqbal Ali , Keith A. Joyner , Yin Hu , Jeffrey Alan McKee , Peter Stewart McAnally
发明人： Amitava Chatterjee , Theodore W. Houston , Ih-Chin Chen , Agerico L. Esquirel , Somnath Nag , Iqbal Ali , Keith A. Joyner , Yin Hu , Jeffrey Alan McKee , Peter Stewart McAnally
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3105 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.
摘要翻译：制造半导体器件或集成电路的技术产生平坦化的补充层，其在抛光之后具有比较均匀的厚度，例如通过化学机械抛光（CMP）。在通常由场氧化物占据的衬底的该部分中的有源区域之间插入虚拟有源区，以便在这些区域中减少在CMP期间发生的“凹陷”。虚拟有源区域可以采取大块，部分或完全形成的环形结构的形状，或者可以调节其面积密度以匹配衬底的该区域中的有源区的面积密度的多个柱。支柱的设计规则可以是在多晶硅线或第一级金属化线被放置以避免寄生电容的地方放置柱子。

8. 发明授权

US4882649A Nitride/oxide/nitride capacitor dielectric 失效
标题翻译：氮化物/氧化物/氮化物电容器电介质
公开(公告)号：US4882649A
公开(公告)日：1989-11-21
申请号：US174751
申请日：1988-03-29
申请人： Ih-Chin Chen , Bing W. Shen , Robert R. Doering
发明人： Ih-Chin Chen , Bing W. Shen , Robert R. Doering
IPC分类号： H01G4/20 , H01L27/108 , H01L29/94
CPC分类号： H01G4/20 , H01L27/10829 , H01L29/945 , Y10T29/435
摘要： An integrated circuit capacitor is disclosed which has improved leakage and storage characteristics. The dielectric material for the capacitor consists of a first layer of silicon nitride adjacent the lower plate, such as a silicon substrate, upon which a layer of silicon dioxide is formed. A second layer of silicon nitride is formed over the silicon dioxide layer, above which the second plate is formed. The layer of silicon dioxide may be formed by the partial oxidation of the first silicon nitride layer. The capacitor may be a planar capacitor, may be formed in a trench, or may be formed between two layers above the surface of the substrate.
摘要翻译：公开了一种具有改进的泄漏和存储特性的集成电路电容器。用于电容器的电介质材料包括邻近下板的第一层氮化硅，例如硅衬底，在其上形成二氧化硅层。在二氧化硅层上形成第二层氮化硅，在其上形成第二板。二氧化硅层可以通过第一氮化硅层的部分氧化形成。电容器可以是平面电容器，可以形成在沟槽中，或者可以形成在衬底表面之上的两层之间。

9. 发明授权

US06287924B1 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06287924B1
公开(公告)日：2001-09-11
申请号：US09407213
申请日：1999-09-28
申请人： Chih-Ping Chao , Ih-Chin Chen , Rick L. Wise , Katherine E. Violette , Sreenath Unnikrishnan
发明人： Chih-Ping Chao , Ih-Chin Chen , Rick L. Wise , Katherine E. Violette , Sreenath Unnikrishnan
IPC分类号： H01L21336
CPC分类号： H01L21/28052 , H01L29/665 , H01L29/66545 , H01L29/66628
摘要： Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.
摘要翻译：使用在硅栅极上方延伸的侧壁间隔物，其中间隔物之间的距离超过栅极的长度用于限制栅极的选择性硅生长和随后的自对准硅化物。

10. 发明授权

US6147384A Method for forming planar field effect transistors with source and drain an insulator and device constructed therefrom 有权
标题翻译：用于形成具有源极和漏极绝缘体的平面场效应晶体管的方法及由其构成的器件
公开(公告)号：US6147384A
公开(公告)日：2000-11-14
申请号：US375994
申请日：1999-08-17
申请人： Ih-Chin Chen
发明人： Ih-Chin Chen
IPC分类号： H01L21/76 , H01L21/31 , H01L21/316 , H01L21/336 , H01L29/06 , H01L29/78 , H01L27/01 , H01L29/76
CPC分类号： H01L29/66651 , H01L29/0653
摘要： A method of forming a field effect transistor with source and drain on an insulator includes forming a first void region (11) in the outer surface of a semiconductor body (10) and forming a second void region (11) in the outer surface of a semiconductor body. The first void region is separated from the second void region by a portion of the semiconductor body (10). The method further includes depositing a dielectric material in the first void region to form a first insulating region (16) and depositing a dielectric material in the second void region to form a second insulating region (16). The method further includes planarizing the first and second insulating regions to define a planar surface (17). The method also includes forming a conductive source region (34) overlying the first insulating region, forming a conductive drain region (36) overlying the second insulating region, and forming a conductive gate body (24) overlying the planar surface and spaced apart from the conductive source region and the conductive drain region.A field effect transistor device (50) having a substrate (10) is provided. The transistor (50) includes a conductive gate body (24) and a gate insulator layer (32) having a planar outer surface adjacent to the conductive gate body and a planar inner surface (39). The transistor further includes first and second insulating regions (16) formed on the substrate. The transistor (50) also includes a conductive drain region (36) formed on the second insulating region and a conductive source region (34) formed on the first insulating region and spaced apart from the conductive gate body (24) opposite the conductive drain region (36). The conductive drain region and conductive source region define a portion of the planar inner surface (39).
摘要翻译：在绝缘体上形成具有源极和漏极的场效应晶体管的方法包括在半导体本体（10）的外表面中形成第一空隙区域（11），并在第二空隙区域（11）的外表面中形成第二空隙区域半导体体。第一空隙区域由半导体本体（10）的一部分与第二空隙区域分离。该方法还包括在第一空隙区域中沉积电介质材料以形成第一绝缘区域（16）并在第二空隙区域中沉积电介质材料以形成第二绝缘区域（16）。该方法还包括平坦化第一和第二绝缘区域以限定平坦表面（17）。该方法还包括形成覆盖第一绝缘区域的导电源区域（34），形成覆盖在第二绝缘区域上的导电漏极区域（36），以及形成覆盖该平面表面并与该平面表面间隔开的导电栅极体（24）导电源区和导电漏极区。提供具有基板（10）的场效应晶体管器件（50）。晶体管（50）包括导电栅极主体（24）和栅极绝缘体层（32），栅极绝缘体层（32）具有与导电栅极主体相邻的平面外表面和平坦的内表面（39）。晶体管还包括形成在衬底上的第一和第二绝缘区域（16）。晶体管（50）还包括形成在第二绝缘区域上的导电漏极区域（36）和形成在第一绝缘区域上并与导电栅极体（24）间隔开的导电源区域（34）（36）。导电漏极区域和导电源区域限定平面内表面（39）的一部分。

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