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1. 发明授权

US06838348B2 Integrated process for high voltage and high performance silicon-on-insulator bipolar devices 有权
标题翻译：用于高电压和高性能绝缘体上的双极器件的集成工艺
公开(公告)号：US06838348B2
公开(公告)日：2005-01-04
申请号：US10844144
申请日：2004-05-12
申请人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
发明人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
IPC分类号： H01L21/331 , H01L21/84 , H01L27/082 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/73
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/0826 , H01L27/1203 , H01L29/0692 , H01L29/0821 , H01L29/7317
摘要： High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.
摘要翻译：公开了绝缘体上硅（SOI）集成电路中的高电压双极晶体管（30,60）。在一个公开的实施例中，集电极区域（28）形成在设置在掩埋绝缘体层（22）上的外延硅（24,25）中。基极区域（32）和发射极（36）设置在集电极区域（28）的上方。掩埋集电极区域（31）设置在远离基极区域（32）的外延硅（24）中。晶体管可以以常规方式布置成矩形方式，或者通过形成环形埋层集电极区域（31）来布置。根据另一公开的实施例，高压晶体管（60）包括中心隔离结构（62），使得基极区域（65）和发射极区域（66）是环形的，以提供改进的性能。还公开了与高性能晶体管（40）同时制造高压晶体管（30,60）的工艺。

2. 发明申请

US20100163997A1 EPITAXIAL DEPOSITION-BASED PROCESSES FOR REDUCING GATE DIELECTRIC THINNING AT TRENCH EDGES AND INTEGRATED CIRCUITS THEREFROM 有权
标题翻译：用于降低栅极电介质薄膜和其集成电路中的栅极介电沉积的基于外延沉积的工艺
公开(公告)号：US20100163997A1
公开(公告)日：2010-07-01
申请号：US12344995
申请日：2008-12-29
申请人： Vladimir F. DROBNY , Amitava CHATTERJEE , Phillipp STEINMANN , Rick WISE
发明人： Vladimir F. DROBNY , Amitava CHATTERJEE , Phillipp STEINMANN , Rick WISE
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L21/28123 , H01L21/76229 , H01L21/823481 , H01L21/823878 , H01L29/1087 , H01L29/66651
摘要： A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed.
摘要翻译：一种制造集成电路（IC）及其IC的方法，包括多个金属氧化物半导体（MOS）晶体管，其栅极电介质薄膜在沟槽隔离/半导体边缘处具有减小的栅极电介质薄化和拐角锐化，用于通常为500至5000埃厚的栅极电介质层。该方法包括提供具有包含硅的表面的衬底。在衬底中形成多个电介质填充沟槽隔离区。包括表面的硅在其周边与沟槽隔离区形成沟槽隔离有源区边缘。沉积外延硅层，其中包含硅层的外延形成在包含硅的表面上。包含硅层的外延被氧化以将至少一部分转化成热生长的氧化硅层，其中热生长的氧化硅层为所述多个MOS晶体管中的至少一个提供至少一部分栅极电介质层。在栅极电介质上形成图案化的栅极电极层，其中图案化的栅极电极层在沟槽隔离有源区域边缘中的至少一个上延伸。然后完成IC的制造。

3. 发明授权

US06660616B2 P-i-n transit time silicon-on-insulator device 有权
公开(公告)号：US06660616B2
公开(公告)日：2003-12-09
申请号：US10055436
申请日：2002-01-23
申请人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann
发明人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann
IPC分类号： H01L2120
CPC分类号： H01L29/868
摘要： A transit time device (15, 15′) in a silicon-on-insulator (SOI) technology is disclosed. An anode region (18) and a cathode region (20) are formed on opposing ends of an epitaxial layer (14), with an intrinsic or lightly-doped region (22) disposed therebetween. Sinker structures (30p, 30n) are formed in an overlying epitaxial layer (24) over and in contact with the anode and cathode regions (18, 20). A charge injection terminal may be formed in a sinker structure (32n) in the overlying epitaxial layer (24), if the transit time device (15′) is of the three-terminal type. The device (15, 15′) has extremely low parasitic capacitance to substrate, because of the buried oxide layer (12) underlying the intrinsic region (22).

4. 发明授权

US08053322B2 Epitaxial deposition-based processes for reducing gate dielectric thinning at trench edges and integrated circuits therefrom 有权
标题翻译：用于减小沟槽边缘处栅极电介质薄化的外延沉积工艺及其集成电路
公开(公告)号：US08053322B2
公开(公告)日：2011-11-08
申请号：US12344995
申请日：2008-12-29
申请人： Vladimir F. Drobny , Amitava Chatterjee , Phillipp Steinmann , Rick Wise
发明人： Vladimir F. Drobny , Amitava Chatterjee , Phillipp Steinmann , Rick Wise
IPC分类号： H01L21/336
CPC分类号： H01L21/28123 , H01L21/76229 , H01L21/823481 , H01L21/823878 , H01L29/1087 , H01L29/66651
摘要： A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed.
摘要翻译：一种制造集成电路（IC）及其IC的方法，包括多个金属氧化物半导体（MOS）晶体管，其栅极电介质薄膜在沟槽隔离/半导体边缘处具有减小的栅极电介质薄化和拐角锐化，用于通常为500至5000埃厚的栅极电介质层。该方法包括提供具有包含硅的表面的衬底。在衬底中形成多个电介质填充沟槽隔离区。包括表面的硅在其周边与沟槽隔离区形成沟槽隔离有源区边缘。沉积外延硅层，其中包含硅层的外延形成在包含硅的表面上。包含硅层的外延被氧化以将至少一部分转化成热生长的氧化硅层，其中热生长的氧化硅层为所述多个MOS晶体管中的至少一个提供至少一部分栅极电介质层。在栅极电介质上形成图案化的栅极电极层，其中图案化的栅极电极层在沟槽隔离有源区域边缘中的至少一个上延伸。然后完成IC的制造。

5. 发明授权

US06770952B2 Integrated process for high voltage and high performance silicon-on-insulator bipolar devices 有权
公开(公告)号：US06770952B2
公开(公告)日：2004-08-03
申请号：US10132817
申请日：2002-04-25
申请人： Jeffrey A. Babcock , Gregory E Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
发明人： Jeffrey A. Babcock , Gregory E Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
IPC分类号： H01L27082
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/0826 , H01L27/1203 , H01L29/0692 , H01L29/0821 , H01L29/7317
摘要： High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

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