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    • 3. 发明授权
      US6028797A Multi-bank integrated circuit memory devices having cross-coupled isolation and precharge circuits therein 有权
    • Multi-bank integrated circuit memory devices having cross-coupled isolation and precharge circuits therein
    • 在其中具有交叉耦合隔离和预充电电路的多存储体集成电路存储器件
    • US6028797A
    • 2000-02-22
    • US196991
    • 1998-11-20
    • Gwang-young Kim , Jong-hyoung Lim , Sang-seok Kang
    • Gwang-young Kim , Jong-hyoung Lim , Sang-seok Kang
    • G11C11/41 , G11C7/06 , G11C7/10 , G11C7/12 , G11C11/34 , G11C11/401 , G11C11/409 , G11C7/00
    • G11C7/1042 , G11C7/06 , G11C7/12 , G11C2207/12
    • Multi-bank integrated circuit memory devices include first and second memory cell arrays having first and second pairs of differential bit lines electrically coupled thereto, respectively. A dual sense amplifier is also provided and this sense amplifier is electrically coupled together by a first pair of differential input/output lines. First and second isolation circuits are also provided. The first isolation circuit is electrically coupled to the first pair of differential bit lines and is responsive to a first control signal (C1). The second isolation circuit is electrically coupled to the second pair of differential bit lines and is responsive to a second control signal (C2). First and second equalization circuits are provided. The first equalization circuit is responsive to the second control signal and performs the function of equalizing a potential of the first pair of differential bit lines. The second equalization circuit is responsive to the first control signal and performs the function of equalizing a potential of the second pair of differential bit lines. These first and second control signals are generated by a control signal generator, in response to a row address.
    • 多组集成电路存储器件包括分别与其电耦合的第一和第二对差分位线的第一和第二存储单元阵列。 还提供双重放大器，并且该读出放大器通过第一对差分输入/输出线电耦合在一起。 还提供了第一和第二隔离电路。 第一隔离电路电耦合到第一对差分位线，并响应于第一控制信号（C1）。 第二隔离电路电耦合到第二对差分位线，并响应于第二控制信号（C2）。 提供第一和第二均衡电路。 第一均衡电路响应于第二控制信号，并且执行均衡第一对差分位线的电位的功能。 第二均衡电路响应于第一控制信号，并且执行均衡第二对差分位线的电位的功能。 响应于行地址，这些第一和第二控制信号由控制信号发生器产生。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 5. 发明授权
      US5949724A Burn-in stress circuit for semiconductor memory device 失效
    • Burn-in stress circuit for semiconductor memory device
    • 半导体存储器件的老化应力电路
    • US5949724A
    • 1999-09-07
    • US858769
    • 1997-05-19
    • Sang-seok Kang , Jae-hoon Joo , Kyung-moo Kim , Byung-heon Kwak
    • Sang-seok Kang , Jae-hoon Joo , Kyung-moo Kim , Byung-heon Kwak
    • G01R31/28 , G11C11/401 , G11C11/407 , G11C29/06 , G11C29/34 , G11C7/00
    • G11C29/34
    • A burn-in stress circuit for a semiconductor memory device. A burn-in enable signal generator generates a burn-in enable signal in response to a plurality of control signals. A wordline predecoder generates a wordline driving voltage for driving a wordline in response to the burn-in enable signal and another a plurality of control signals. A wordline decoder applies the wordline driving voltage to the wordline in response to the burn-in enable signal and another plurality of control signals. To reduce the stress testing time by stressing multiple rows of a memory array simultaneously, all of the wordlines (rows) are stressed and or tested at the same time. To select all of the wordlines, the wordlines are selected sequentially, but each selected wordline is held in a selected state by a latching mechanism while all of the other wordlines are being selected as well. When all of the wordlines (or a desired subset) have been selected, the burn-in stress test begins.
    • 一种用于半导体存储器件的老化应力电路。 老化启动信号发生器响应于多个控制信号产生老化启用信号。 字线预解码器响应于老化允许信号和另一个多个控制信号产生用于驱动字线的字线驱动电压。 字线解码器响应于老化启用信号和另外多个控制信号将字线驱动电压施加到字线。 为了通过同时强调多行存储器阵列来减少压力测试时间，所有字线（行）都被同时强调和/或测试。 为了选择所有字线，顺序地选择字线，但是通过锁存机构将所选择的每个字线保持在选择状态，同时也选择所有其他字线。 当所有字线（或所需的子集）都被选择时，老化压力测试开始。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US5929696A Circuit for converting internal voltage of semiconductor device 失效
    • Circuit for converting internal voltage of semiconductor device
    • 用于转换半导体器件内部电压的电路
    • US5929696A
    • 1999-07-27
    • US953052
    • 1997-10-17
    • Jong-Hyoung Lim , Jae-hoon Joo , Sang-seok Kang , Jin-seok Lee
    • Jong-Hyoung Lim , Jae-hoon Joo , Sang-seok Kang , Jin-seok Lee
    • G11C11/413 , G05F1/46 , G11C11/401 , G11C11/407 , G11C29/06 , H01L27/10 , G05F1/10
    • G05F1/465
    • An internal voltage conversion circuit for a DRAM wherein a voltage level of an internal power supply is regulated by an external signal applied to the DRAM pins after packaging to perform reliability tests. The internal voltage conversion circuit includes a test mode signal generator, for generating a test mode signal by combining first control signals applied externally of the semiconductor device, and a switching signal generator, for generating first and second switching signals according to second control signals applied externally of the DRAM when the test mode signal is active. First and second switching resistor portions connected in series between the internal power supply port and a ground potential are switched by the first and second switching signals, respectively, so that their resistance values are changed. The resistor portions are in a feedback path connected to one input of a comparator. The other input is connected to a reference cell. The internal voltage supply varies responsive to changes in resistance values.
    • 一种用于DRAM的内部电压转换电路，其中内部电源的电压电平通过在封装之后施加到DRAM引脚的外部信号进行调节以执行可靠性测试。 内部电压转换电路包括测试模式信号发生器，用于通过组合在半导体器件外部施加的第一控制信号和开关信号发生器产生测试模式信号，用于根据外部施加的第二控制信号产生第一和第二开关信号 当测试模式信号有效时。 串联连接在内部电源端口和接地电位之间的第一和第二开关电阻部分分别通过第一和第二开关信号切换，使得它们的电阻值被改变。 电阻器部分处于连接到比较器的一个输入端的反馈路径中。 另一个输入连接到参考单元。 内部电压供应根据电阻值的变化而变化。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5867434A Integrated circuit memory devices having dummy memory cells therein for inhibiting memory failures 失效
    • Integrated circuit memory devices having dummy memory cells therein for inhibiting memory failures
    • 具有用于抑制存储器故障的虚拟存储器单元的集成电路存储器件
    • US5867434A
    • 1999-02-02
    • US912486
    • 1997-08-18
    • Chang-hag Oh , Sang-seok Kang , Jeon-hyung Lee , Jin-seok Lee
    • Chang-hag Oh , Sang-seok Kang , Jeon-hyung Lee , Jin-seok Lee
    • H01L27/10 , H01L27/108 , G11C7/00
    • H01L27/10897
    • Integrated circuit memory devices contain an array of active memory cells and at least one column of dummy memory cells having missing electrical connections to either a dummy bit line and/or respective storage electrodes. The dummy memory cells are provided with missing electrical connections so that formation of stray electrical "shorts" between storage electrodes of dummy and active memory cells during fabrication do not cause memory failures when the memory devices are installed. In particular, integrated circuit memory devices are provided which comprise an array of active DRAM memory cells and a column of dummy DRAM memory cells. The active DRAM memory cells each contain electrical connections to a respective active bit line and a respective storage electrode, but the dummy DRAM memory cells are each devoid of an electrical connection to a dummy bit line and/or a respective storage electrode. Accordingly, the formation of a stringer (e.g., electrical short) between a storage capacitor of an active memory cell and a dummy memory cell does not result in a memory failure even if the word line coupled to the dummy memory cell is activated and the dummy bit line is biased at a potential which is different from the potential of the storage capacitor of the active memory cell.
    • 集成电路存储器件包含有效存储器单元的阵列和至少一列虚拟存储器单元，其具有与虚拟位线和/或相应存储电极的缺失的电连接。 虚拟存储器单元被提供有缺失的电连接，使得在制造期间在虚拟存储单元和有源存储单元的存储电极之间形成杂散电“短路”在安装存储器件时不会引起存储器故障。 特别地，提供了包括有源DRAM存储器单元阵列和虚拟DRAM存储器单元的列的集成电路存储器件。 有源DRAM存储单元各自包含与相应的有源位线和相应的存储电极的电连接，但虚拟DRAM存储单元各自没有与虚拟位线和/或相应存储电极的电连接。 因此，即使连接到虚拟存储器单元的字线被激活，在活动存储单元的存储电容器和虚拟存储单元之间形成纵梁（例如电短路）也不会导致存储器故障，并且虚拟 位线偏置于与有源存储单元的存储电容器的电位不同的电位。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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