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1. 发明授权

US06225818B1 Integrated circuits including function identification circuits having operating modes that identify corresponding functions of the integrated circuits 失效
标题翻译：集成电路包括具有识别集成电路的相应功能的操作模式的功能识别电路
公开(公告)号：US06225818B1
公开(公告)日：2001-05-01
申请号：US09304030
申请日：1999-05-03
申请人： Cheol-hong Park , Sang-seok Kang , Jae-hoon Joo
发明人： Cheol-hong Park , Sang-seok Kang , Jae-hoon Joo
IPC分类号： G01R3102
CPC分类号： H01L23/544 , G01R31/2884 , G06F11/006 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit includes first and second pads that are electrically connected to a circuit inside the integrated circuit. The circuit performs multiple functions which may be selected. A function identification circuit, inside the integrated circuit, is electrically connected to the first and second pads. The function identification circuit operates in multiple modes, wherein each operating mode corresponds to a function performed by the circuit. The function of the circuit may thereby be identified using fewer pads which may allow a reduction in the cost of the integrated circuit.
摘要翻译：集成电路包括电连接到集成电路内的电路的第一和第二焊盘。电路执行可以选择的多种功能。集成电路内部的功能识别电路电连接到第一和第二焊盘。功能识别电路以多种模式工作，其中每个操作模式对应于由电路执行的功能。因此，可以使用更少的焊盘来识别电路的功能，这可以允许降低集成电路的成本。

2. 发明授权

US5949724A Burn-in stress circuit for semiconductor memory device 失效
标题翻译：半导体存储器件的老化应力电路
公开(公告)号：US5949724A
公开(公告)日：1999-09-07
申请号：US858769
申请日：1997-05-19
申请人： Sang-seok Kang , Jae-hoon Joo , Kyung-moo Kim , Byung-heon Kwak
发明人： Sang-seok Kang , Jae-hoon Joo , Kyung-moo Kim , Byung-heon Kwak
IPC分类号： G01R31/28 , G11C11/401 , G11C11/407 , G11C29/06 , G11C29/34 , G11C7/00
CPC分类号： G11C29/34
摘要： A burn-in stress circuit for a semiconductor memory device. A burn-in enable signal generator generates a burn-in enable signal in response to a plurality of control signals. A wordline predecoder generates a wordline driving voltage for driving a wordline in response to the burn-in enable signal and another a plurality of control signals. A wordline decoder applies the wordline driving voltage to the wordline in response to the burn-in enable signal and another plurality of control signals. To reduce the stress testing time by stressing multiple rows of a memory array simultaneously, all of the wordlines (rows) are stressed and or tested at the same time. To select all of the wordlines, the wordlines are selected sequentially, but each selected wordline is held in a selected state by a latching mechanism while all of the other wordlines are being selected as well. When all of the wordlines (or a desired subset) have been selected, the burn-in stress test begins.
摘要翻译：一种用于半导体存储器件的老化应力电路。老化启动信号发生器响应于多个控制信号产生老化启用信号。字线预解码器响应于老化允许信号和另一个多个控制信号产生用于驱动字线的字线驱动电压。字线解码器响应于老化启用信号和另外多个控制信号将字线驱动电压施加到字线。为了通过同时强调多行存储器阵列来减少压力测试时间，所有字线（行）都被同时强调和/或测试。为了选择所有字线，顺序地选择字线，但是通过锁存机构将所选择的每个字线保持在选择状态，同时也选择所有其他字线。当所有字线（或所需的子集）都被选择时，老化压力测试开始。

3. 发明授权

US5929696A Circuit for converting internal voltage of semiconductor device 失效
标题翻译：用于转换半导体器件内部电压的电路
公开(公告)号：US5929696A
公开(公告)日：1999-07-27
申请号：US953052
申请日：1997-10-17
申请人： Jong-Hyoung Lim , Jae-hoon Joo , Sang-seok Kang , Jin-seok Lee
发明人： Jong-Hyoung Lim , Jae-hoon Joo , Sang-seok Kang , Jin-seok Lee
IPC分类号： G11C11/413 , G05F1/46 , G11C11/401 , G11C11/407 , G11C29/06 , H01L27/10 , G05F1/10
CPC分类号： G05F1/465
摘要： An internal voltage conversion circuit for a DRAM wherein a voltage level of an internal power supply is regulated by an external signal applied to the DRAM pins after packaging to perform reliability tests. The internal voltage conversion circuit includes a test mode signal generator, for generating a test mode signal by combining first control signals applied externally of the semiconductor device, and a switching signal generator, for generating first and second switching signals according to second control signals applied externally of the DRAM when the test mode signal is active. First and second switching resistor portions connected in series between the internal power supply port and a ground potential are switched by the first and second switching signals, respectively, so that their resistance values are changed. The resistor portions are in a feedback path connected to one input of a comparator. The other input is connected to a reference cell. The internal voltage supply varies responsive to changes in resistance values.
摘要翻译：一种用于DRAM的内部电压转换电路，其中内部电源的电压电平通过在封装之后施加到DRAM引脚的外部信号进行调节以执行可靠性测试。内部电压转换电路包括测试模式信号发生器，用于通过组合在半导体器件外部施加的第一控制信号和开关信号发生器产生测试模式信号，用于根据外部施加的第二控制信号产生第一和第二开关信号当测试模式信号有效时。串联连接在内部电源端口和接地电位之间的第一和第二开关电阻部分分别通过第一和第二开关信号切换，使得它们的电阻值被改变。电阻器部分处于连接到比较器的一个输入端的反馈路径中。另一个输入连接到参考单元。内部电压供应根据电阻值的变化而变化。

4. 发明授权

US07460428B2 Dynamic random access memory and communications terminal including the same 有权
标题翻译：动态随机存取存储器和通信终端包括相同
公开(公告)号：US07460428B2
公开(公告)日：2008-12-02
申请号：US11482141
申请日：2006-07-07
申请人： Jae-hoon Joo , Sang-seok Kang , Byung-heon Kwak , Kang-young Cho , Chang-hag Oh
发明人： Jae-hoon Joo , Sang-seok Kang , Byung-heon Kwak , Kang-young Cho , Chang-hag Oh
IPC分类号： G11C7/00
CPC分类号： G11C11/4074 , G11C11/4087 , G11C2207/2227
摘要： Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.
摘要翻译：提供了具有降低的电流消耗的DRAM和包括该DRAM的通信终端。 DRAM包括能够独立地供电的多个存储器组和用于选择性地使多个存储体中的一些存储器进入DPD模式的DPD控制器。

5. 发明申请

US20070008802A1 Dynamic random access memory and communications terminal including the same 有权
标题翻译：动态随机存取存储器和通信终端包括相同
公开(公告)号：US20070008802A1
公开(公告)日：2007-01-11
申请号：US11482141
申请日：2006-07-07
申请人： Jae-hoon Joo , Sang-seok Kang , Byung-heon Kwak , Kang-young Cho , Chang-hag Oh
发明人： Jae-hoon Joo , Sang-seok Kang , Byung-heon Kwak , Kang-young Cho , Chang-hag Oh
IPC分类号： G11C5/14
CPC分类号： G11C11/4074 , G11C11/4087 , G11C2207/2227
摘要： Provided is a DRAM having reduced current consumption and a communication terminal including the same. The DRAM includes a plurality of memory banks capable of being independently supplied with power, and a DPD controller for selectively causing some of the plurality of memory banks to enter a DPD mode.
摘要翻译：提供了具有降低的电流消耗的DRAM和包括该DRAM的通信终端。 DRAM包括能够独立地供电的多个存储器组和用于选择性地使多个存储体中的一些存储器进入DPD模式的DPD控制器。

6. 发明授权

US06215723B1 Semiconductor memory device having sequentially disabling activated word lines 有权
标题翻译：具有顺序禁用激活字线的半导体存储器件
公开(公告)号：US06215723B1
公开(公告)日：2001-04-10
申请号：US09489236
申请日：2000-01-21
申请人： Sang-seok Kang , Jae-hoon Joo
发明人： Sang-seok Kang , Jae-hoon Joo
IPC分类号： G11C800
CPC分类号： G11C11/4087 , G11C8/04 , G11C8/10 , G11C11/4085
摘要： A semiconductor memory device for sequentially disabling activated word lines is provided. The semiconductor memory device having a plurality of word lines connected to a plurality of memory cells includes a predecoding unit for predecoding a row address received from the outside, a row decoding and word line driving block, which is connected to the predecoding unit and the plurality of word lines, for decoding an output of the predecoding unit, selecting some of the plurality of word lines, and activating the selected word lines and a controller connected to the predecoding unit and the row decoding and word line driving block, for receiving the row address, the output of the predecoding unit, and at least one control signal, generating at least one output signal, and sequentially disabling the activated word lines by enabling the at least one output signal in response to the row address and the output of the predecoding unit.
摘要翻译：提供了用于顺序禁用激活字线的半导体存储器件。具有连接到多个存储单元的多个字线的半导体存储器件包括预解码单元，用于对从外部接收的行地址进行预编码，行解码和字线驱动块，其连接到预解码单元和多个的字线，用于解码预解码单元的输出，选择多个字线中的一些，并激活所选择的字线，以及连接到预解码单元和行解码和字线驱动块的控制器，用于接收行地址，预解码单元的输出，以及至少一个控制信号，产生至少一个输出信号，以及通过响应于行地址和预解码的输出启用至少一个输出信号来顺序地禁用激活的字线单元。

7. 发明授权

US6028797A Multi-bank integrated circuit memory devices having cross-coupled isolation and precharge circuits therein 有权
标题翻译：在其中具有交叉耦合隔离和预充电电路的多存储体集成电路存储器件
公开(公告)号：US6028797A
公开(公告)日：2000-02-22
申请号：US196991
申请日：1998-11-20
申请人： Gwang-young Kim , Jong-hyoung Lim , Sang-seok Kang
发明人： Gwang-young Kim , Jong-hyoung Lim , Sang-seok Kang
IPC分类号： G11C11/41 , G11C7/06 , G11C7/10 , G11C7/12 , G11C11/34 , G11C11/401 , G11C11/409 , G11C7/00
CPC分类号： G11C7/1042 , G11C7/06 , G11C7/12 , G11C2207/12
摘要： Multi-bank integrated circuit memory devices include first and second memory cell arrays having first and second pairs of differential bit lines electrically coupled thereto, respectively. A dual sense amplifier is also provided and this sense amplifier is electrically coupled together by a first pair of differential input/output lines. First and second isolation circuits are also provided. The first isolation circuit is electrically coupled to the first pair of differential bit lines and is responsive to a first control signal (C1). The second isolation circuit is electrically coupled to the second pair of differential bit lines and is responsive to a second control signal (C2). First and second equalization circuits are provided. The first equalization circuit is responsive to the second control signal and performs the function of equalizing a potential of the first pair of differential bit lines. The second equalization circuit is responsive to the first control signal and performs the function of equalizing a potential of the second pair of differential bit lines. These first and second control signals are generated by a control signal generator, in response to a row address.
摘要翻译：多组集成电路存储器件包括分别与其电耦合的第一和第二对差分位线的第一和第二存储单元阵列。还提供双重放大器，并且该读出放大器通过第一对差分输入/输出线电耦合在一起。还提供了第一和第二隔离电路。第一隔离电路电耦合到第一对差分位线，并响应于第一控制信号（C1）。第二隔离电路电耦合到第二对差分位线，并响应于第二控制信号（C2）。提供第一和第二均衡电路。第一均衡电路响应于第二控制信号，并且执行均衡第一对差分位线的电位的功能。第二均衡电路响应于第一控制信号，并且执行均衡第二对差分位线的电位的功能。响应于行地址，这些第一和第二控制信号由控制信号发生器产生。

8. 发明授权

US06898139B2 Integrated circuit memory devices and operating methods that are configured to output data bits at a lower rate in a test mode of operation 有权
标题翻译：集成电路存储器件和操作方法，被配置为在测试操作模式下以较低的速率输出数据位
公开(公告)号：US06898139B2
公开(公告)日：2005-05-24
申请号：US10773024
申请日：2004-02-05
申请人： Jae-woong Lee , Chi-wook Kim , Sang-seok Kang
发明人： Jae-woong Lee , Chi-wook Kim , Sang-seok Kang
IPC分类号： G11C11/40 , G11C7/10 , G11C7/22 , G11C29/14 , G11C7/00
CPC分类号： G11C29/12015 , G11C7/1051 , G11C7/22 , G11C29/14
摘要： Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.
摘要翻译：集成电路存储器件包括被配置为以第一数据速率并行输出数据位的存储单元阵列。输出电路被配置为在正常操作模式下以第一数据速率将数据位串行地输出到外部终端，并且以低于第一数据的第二数据速率将数据位串行输出到外部终端在测试操作模式下的速率。因此，在测试操作模式下，存储单元阵列可以以第一数据速率工作，同时允许输出电路以低于第一数据速率的第二数据速率将数据输出到外部终端。

9. 发明授权

US06850450B2 Fuse box including make-link and redundant address decoder having the same, and method for repairing defective memory cell 失效
标题翻译：包括制造链路和具有相同功能的冗余地址解码器的保险丝盒以及用于修复有缺陷的存储器单元的方法
公开(公告)号：US06850450B2
公开(公告)日：2005-02-01
申请号：US10075568
申请日：2002-02-13
申请人： Kwang-kyu Bang , Kyeong-seon Shin , Sang-seok Kang , Hyen-wook Ju , Jeong-ho Bang , Ho-Jeong Choi
发明人： Kwang-kyu Bang , Kyeong-seon Shin , Sang-seok Kang , Hyen-wook Ju , Jeong-ho Bang , Ho-Jeong Choi
IPC分类号： G11C29/00 , G11C11/00
CPC分类号： G11C29/785 , G11C29/781
摘要： A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.
摘要翻译：提供包括制造链路的保险丝盒和包括保险丝盒的冗余地址解码器。优选地，保险丝盒包括多个制造链接，用于通过对应的冗余存储器单元的地址对有缺陷的正常存储器单元的地址进行编程，并且该地址是行地址或列地址。冗余地址解码器包括具有用于对缺陷单元的地址进行解码的多个制造链路的熔丝盒和冗余字线选择电路，用于响应于对应于缺陷单元的地址的冗余单元的字线进行选择从保险丝盒输出的信号。

10. 发明授权

US06861682B2 Laser link structure capable of preventing an upper crack and broadening an energy window of a laser beam, and fuse box using the same 有权
标题翻译：激光连接结构能够防止上部裂纹和加宽激光束的能量窗口，以及使用其的保险丝盒
公开(公告)号：US06861682B2
公开(公告)日：2005-03-01
申请号：US10290269
申请日：2002-11-08
申请人： Jeong-ho Bang , Kyeong-seon Shin , Sang-seok Kang , Ho-jeong Choi , Hyen-wook Ju , Kwang-kyu Bang
发明人： Jeong-ho Bang , Kyeong-seon Shin , Sang-seok Kang , Ho-jeong Choi , Hyen-wook Ju , Kwang-kyu Bang
IPC分类号： G11C17/18 , G11C17/14 , G11C29/00 , G11C29/04 , H01L21/82 , H01L23/525 , H01L27/10
CPC分类号： G11C17/14 , G11C29/785 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A laser link structure used in semiconductor devices and a fuse box using the laser link structure preferably include a plurality of first conductive line patterns positioned in parallel at predetermined intervals, and a second conductive line pattern broadly formed on the plurality of first conductive line patterns for forming hole regions which link the second conductive line pattern to the plurality of first conductive line patterns. Preferably, at least one hole region is formed on each of the plurality of first conductive line patterns, and via holes are formed in the hole regions.
摘要翻译：在半导体器件中使用的激光连接结构和使用激光连接结构的熔丝盒优选地包括以预定间隔平行定位的多个第一导电线图案，以及广泛地形成在多个第一导电线图案上的第二导电线图案，形成将所述第二导电线图案连接到所述多个第一导电线图案的孔区域。优选地，在多个第一导电线图案中的每一个上形成至少一个孔区，并且在孔区中形成通孔。

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