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1. 发明授权

US11862271B2 Memory testing techniques 有权
公开(公告)号：US11862271B2
公开(公告)日：2024-01-02
申请号：US16418833
申请日：2019-05-21
申请人： Arm Limited
发明人： Andy Wangkun Chen , Yannis Jallamion-Grive , Cyrille Nicolas Dray
IPC分类号： G11C29/00 , G11C29/42 , G06F11/27 , G06F11/10 , G11C29/34 , G11C29/02 , G11C29/18
CPC分类号： G11C29/42 , G06F11/102 , G06F11/106 , G06F11/27 , G11C29/025 , G11C29/34 , G11C29/781 , G11C29/802 , G11C2029/1802
摘要： Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

2. 发明授权

US10490246B2 Semiconductor device and semiconductor system 有权
公开(公告)号：US10490246B2
公开(公告)日：2019-11-26
申请号：US15624458
申请日：2017-06-15
申请人： SK hynix Inc.
发明人： Sang Hyun Ku , HongJung Kim
IPC分类号： G11C8/10 , G11C8/18 , G11C29/00 , G11C8/12 , G11C17/16 , G11C29/12
CPC分类号： G11C8/18 , G11C8/10 , G11C8/12 , G11C17/16 , G11C29/76 , G11C29/781 , G11C29/832 , G11C29/84 , G11C29/835 , G11C2029/1202
摘要： A semiconductor system includes a first semiconductor device and a first semiconductor device. The first semiconductor device outputs a clock, a chip selection signal and addresses. The second semiconductor device generates a masking signal from the addresses inputted in synchronization with a first pulse of the clock in response to the chip selection signal and decodes internal addresses generated from the addresses inputted in synchronization with a second pulse of the clock to select a word line. The second semiconductor device controls a connection between an address decoder and a fuse circuit in response to the masking signal. The address decoder selects the word line.

3. 发明申请

US20180240534A1 MEMORY APPARATUS WITH POST PACKAGE REPAIR 有权
公开(公告)号：US20180240534A1
公开(公告)日：2018-08-23
申请号：US15714752
申请日：2017-09-25
申请人： MICRON TECHNOLOGY, INC.
发明人： Hideyuki Yoko
IPC分类号： G11C29/00 , G11C17/18 , G11C17/16
CPC分类号： G11C29/78 , G11C17/16 , G11C17/18 , G11C29/12005 , G11C29/44 , G11C29/702 , G11C29/72 , G11C29/76 , G11C29/781 , G11C29/785 , G11C29/789
摘要： Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a storage latch circuit coupled to the non-volatile storage element and stores latch information; and a control circuit that, in a first repair mode, receives first repair address information, provides the first repair address information to the non-volatile storage element, and further transmits the first repair address information from the non-volatile storage element to the storage latch circuit. The control circuit, in a second repair mode, receives second repair address information and provides the second repair address information to the storage latch circuit and disables storing the second address information into the non-volatile storage element.

4. 发明申请

US20180102185A1 FUSE CIRCUIT, REPAIR CONTROL CIRCUIT, AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME 审中-公开
公开(公告)号：US20180102185A1
公开(公告)日：2018-04-12
申请号：US15485921
申请日：2017-04-12
申请人： SK hynix Inc.
发明人： Jong Yeol YANG
IPC分类号： G11C29/00 , G11C17/16 , G11C17/18
CPC分类号： G11C29/78 , G11C5/025 , G11C5/063 , G11C17/16 , G11C17/18 , G11C29/76 , G11C29/781 , G11C29/785 , G11C29/789
摘要： A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. The plurality of second fuse sets may be used to store a defect address detected after the packaging. The plurality of first fuse sets may be shared by a plurality of first redundant word lines, and the plurality of second fuse sets may be in one-to-one correspondence with a plurality of second redundant word lines.

5. 发明授权

US09627095B1 Memory module, memory system including the same and operation method thereof 有权
公开(公告)号：US09627095B1
公开(公告)日：2017-04-18
申请号：US15230122
申请日：2016-08-05
申请人： SK hynix Inc.
发明人： Jing-Zhe Xu , Yong-Ju Kim , Jung-Hyun Kwon , Sung-Eun Lee , Jae-Sun Lee
IPC分类号： G11C29/00 , G11C11/4074 , G11C11/4076 , G11C11/4093 , G11C11/408 , G11C11/4094 , G11C17/16
CPC分类号： G11C29/76 , G06F12/0246 , G11C5/04 , G11C11/4076 , G11C11/4087 , G11C11/4093 , G11C17/16 , G11C29/72 , G11C29/78 , G11C29/781 , G11C29/808 , G11C29/814 , G11C29/832 , G11C29/84 , G11C29/886
摘要： A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.

6. 发明申请

US20160293277A1 MEMORY DEVICE WITH REDUNDANT IO CIRCUIT 有权
标题翻译：具有冗余IO电路的存储器件
公开(公告)号：US20160293277A1
公开(公告)日：2016-10-06
申请号：US15076416
申请日：2016-03-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Atul KATOCH
IPC分类号： G11C29/00 , G11C29/04
CPC分类号： G11C29/781 , G11C2029/4402
摘要： A device includes input/output (IO) circuits, a redundant IO circuit and a redundant IO control unit. The input/output (IO) circuits coupled to a memory array. The redundant IO circuit is coupled to the memory array and the plurality of IO circuits. The redundant IO control unit is coupled to the IO circuits and the redundant IO circuit. In response to a failure column address signal, the redundant IO control unit configures the redundant IO circuit to substitute a failed IO circuit of the IO circuits. The redundant IO control unit includes a storage circuit, and during a shutdown mode, the storage circuit is configured to store the failure column address signal.
摘要翻译：器件包括输入/输出（IO）电路，冗余IO电路和冗余IO控制单元。耦合到存储器阵列的输入/输出（IO）电路。冗余IO电路耦合到存储器阵列和多个IO电路。冗余IO控制单元耦合到IO电路和冗余IO电路。响应于故障列地址信号，冗余IO控制单元配置冗余IO电路以替代IO电路的故障IO电路。冗余IO控制单元包括存储电路，并且在关闭模式期间，存储电路被配置为存储故障列地址信号。

7. 发明申请

US20160027532A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20160027532A1
公开(公告)日：2016-01-28
申请号：US14569311
申请日：2014-12-12
申请人： SK hynix Inc.
发明人： Sang-Hee KIM
IPC分类号： G11C29/00 , G11C11/406
CPC分类号： G11C29/83 , G11C11/406 , G11C29/781
摘要： A memory device includes a plurality of redundancy word lines each of which is coupled with a plurality of redundancy memory cells, and a redundancy refresh circuit suitable for sequentially refreshing first redundancy word lines that are selected as target word lines for an additional refresh operation among the plurality of the redundancy word lines.
摘要翻译：存储器件包括多个冗余字线，每个冗余字线与多个冗余存储器单元耦合，并且冗余刷新电路适用于顺序刷新被选择作为目标字线的第一冗余字线，用于在多个冗余字线。

8. 发明授权

US07251155B2 Device and method having a memory array storing each bit in multiple memory cells 有权
标题翻译：具有将多个存储单元中的每一位存储的存储器阵列的装置和方法
公开(公告)号：US07251155B2
公开(公告)日：2007-07-31
申请号：US11245725
申请日：2005-10-06
申请人： Michael A. Shore
发明人： Michael A. Shore
IPC分类号： G11C11/24
CPC分类号： G11C8/12 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/403 , G11C11/4082 , G11C11/4085 , G11C11/4087 , G11C29/74 , G11C29/781 , G11C29/783 , G11C29/80 , G11C29/88 , G11C2211/4013
摘要： A memory array is provided, having at least two memory cells accessed for each row address to retain a sufficient electric charge to properly store “1” and “0” bits. For such a memory array, both even and odd row decoders in the array are permanently enabled so that each row address the array receives causes the even row decoder to energize at least one even word line and the odd row decoder to energize at least one odd word line. As a result, at least two memory cells are accessed for each row address so that each “1” or “0” bit is stored as an electric charge in at least two memory cells.
摘要翻译：提供了一种存储器阵列，其具有为每个行地址访问的至少两个存储器单元，以保持足够的电荷以正确地存储“1”和“0”位。对于这样的存储器阵列，阵列中的偶数行解码器和奇数行解码器被永久地启用，使得阵列接收的每个行地址使得偶数行解码器激励至少一个偶数字线，并且奇数行解码器激励至少一个奇数字线。结果，对于每个行地址访问至少两个存储单元，使得每个“1”或“0”位作为电荷存储在至少两个存储单元中。

9. 发明授权

US07239564B2 Semiconductor device for rectifying memory defects 有权
标题翻译：用于整流存储器缺陷的半导体器件
公开(公告)号：US07239564B2
公开(公告)日：2007-07-03
申请号：US10989550
申请日：2004-11-17
申请人： Kohei Mutaguchi
发明人： Kohei Mutaguchi
IPC分类号： G11C29/00 , G11C7/00 , G01R31/28
CPC分类号： G11C29/781 , G11C7/20
摘要： The present invention provides a high-capacity and reliable semiconductor device which does not require additional circuits for use at power ON/OFF, additional steps nor high manufacturing cost, and which has a rectifier means for rectifying a defect easily. A semiconductor device comprises a first memory means including a memory cell and a redundant memory cell each including a memory element in the region where a bit line and a word line cross each other with an insulator interposed therebetween, a second memory means for storing an address of a defective memory in the first memory means, a rectifier means including a holding means and a replacement means, and an inspection means for writing data of the second memory means to the holding means. The replacement means replaces the defective memory cell with the redundant memory cell. In addition to the aforementioned four means, a display means for displaying images is provided as well.
摘要翻译：本发明提供了一种高容量且可靠的半导体器件，其不需要用于电源接通/断开的附加电路，附加步骤和制造成本也不高，并且具有用于容易地整流故障的整流器装置。半导体器件包括第一存储器件，其包括存储器单元和冗余存储器单元，每个存储器单元包括存储元件，所述存储器单元位于所述区域中，位线和字线之间插入绝缘体彼此交叉;第二存储器装置，用于存储地址第一存储器装置中的缺陷存储器，包括保持装置和替换装置的整流装置，以及用于将第二存储装置的数据写入保持装置的检查装置。更换装置用冗余存储单元代替有缺陷的存储单元。除了上述四种装置之外，还提供了用于显示图像的显示装置。

10. 发明授权

US07177209B2 Semiconductor memory device and method of driving the same 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US07177209B2
公开(公告)日：2007-02-13
申请号：US10879552
申请日：2004-06-29
申请人： Byoung Jin Choi
发明人： Byoung Jin Choi
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C8/12 , G11C29/781 , G11C29/785
摘要： Provided is directed to a semiconductor memory device and a method of driving the same capable of improving a repair efficiency with comparison to the conventional method which repairs all the redundancy row even when a defective cell is occurred in only one cell, by including: a memory cell array which is comprised of at least more than one redundancy block and redundancy segment by means of dividing it into a plurality of blocks toward a row direction and then dividing the blocks into a plurality of segments; a control circuit for storing a repair information of a defective cell and for repairing the segment generating the defective cell to the redundancy segment according to the repair information by inputting a row address signal and a column address signal.
摘要翻译：本发明涉及一种半导体存储器件及其驱动方法，该半导体存储器件及其驱动方法能够与仅在一个单元中发生缺陷单元时修复所有冗余行的传统方法相比提高修复效率，包括：存储器单元阵列，其由至少一个冗余块和冗余段组成，通过将其划分为多个块朝向行方向，然后将块划分成多个段; 控制电路，用于通过输入行地址信号和列地址信号来存储缺陷单元的修复信息，并根据修复信息修复产生缺陷单元的段到冗余段。

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