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1. 发明授权

US5929696A Circuit for converting internal voltage of semiconductor device 失效
标题翻译：用于转换半导体器件内部电压的电路
公开(公告)号：US5929696A
公开(公告)日：1999-07-27
申请号：US953052
申请日：1997-10-17
申请人： Jong-Hyoung Lim , Jae-hoon Joo , Sang-seok Kang , Jin-seok Lee
发明人： Jong-Hyoung Lim , Jae-hoon Joo , Sang-seok Kang , Jin-seok Lee
IPC分类号： G11C11/413 , G05F1/46 , G11C11/401 , G11C11/407 , G11C29/06 , H01L27/10 , G05F1/10
CPC分类号： G05F1/465
摘要： An internal voltage conversion circuit for a DRAM wherein a voltage level of an internal power supply is regulated by an external signal applied to the DRAM pins after packaging to perform reliability tests. The internal voltage conversion circuit includes a test mode signal generator, for generating a test mode signal by combining first control signals applied externally of the semiconductor device, and a switching signal generator, for generating first and second switching signals according to second control signals applied externally of the DRAM when the test mode signal is active. First and second switching resistor portions connected in series between the internal power supply port and a ground potential are switched by the first and second switching signals, respectively, so that their resistance values are changed. The resistor portions are in a feedback path connected to one input of a comparator. The other input is connected to a reference cell. The internal voltage supply varies responsive to changes in resistance values.
摘要翻译：一种用于DRAM的内部电压转换电路，其中内部电源的电压电平通过在封装之后施加到DRAM引脚的外部信号进行调节以执行可靠性测试。内部电压转换电路包括测试模式信号发生器，用于通过组合在半导体器件外部施加的第一控制信号和开关信号发生器产生测试模式信号，用于根据外部施加的第二控制信号产生第一和第二开关信号当测试模式信号有效时。串联连接在内部电源端口和接地电位之间的第一和第二开关电阻部分分别通过第一和第二开关信号切换，使得它们的电阻值被改变。电阻器部分处于连接到比较器的一个输入端的反馈路径中。另一个输入连接到参考单元。内部电压供应根据电阻值的变化而变化。

2. 发明授权

US06111457A Internal power supply circuit for use in a semiconductor device 失效
标题翻译：用于半导体器件的内部电源电路
公开(公告)号：US06111457A
公开(公告)日：2000-08-29
申请号：US44382
申请日：1998-03-18
申请人： Jong-Hyoung Lim , Sang-Seok Kang , Jae-Hoon Joo , Chang-Joo Choi
发明人： Jong-Hyoung Lim , Sang-Seok Kang , Jae-Hoon Joo , Chang-Joo Choi
IPC分类号： G11C11/413 , G05F1/46 , G05F3/24 , G11C5/14 , G11C11/407 , H01L21/822 , H01L27/04 , G05F3/02
CPC分类号： G05F1/465
摘要： An internal power supply circuit for use in a semiconductor device includes a clamp circuit for clamping an internal voltage to a constant level. The clamped internal voltage is distributed to internal circuits of the semiconductor device through an output node. When the internal voltage rises momentarily due to noise in the internal power supply circuit due to open-circuit phenomenon, the rising internal voltage is discharged through the clamp circuit, thereby maintaining the internal voltage at a constant value. The clamp circuit includes a first transistor for discharging the output node, and a diode-connected transistor for generating a charge voltage at the gate of the first transistor. The threshold voltage of the diode-connected transistor is preferably equal to or lower than the threshold voltage of the first transistor.
摘要翻译：用于半导体器件的内部电源电路包括用于将内部电压钳位到恒定电平的钳位电路。被钳位的内部电压通过输出节点分配给半导体器件的内部电路。当内部电压由于开路现象而由于内部电源电路中的噪声而瞬间上升时，内部电压的上升通过钳位电路放电，从而将内部电压保持在恒定值。钳位电路包括用于对输出节点放电的第一晶体管和用于在第一晶体管的栅极处产生充电电压的二极管连接的晶体管。二极管连接晶体管的阈值电压优选等于或低于第一晶体管的阈值电压。

3. 发明授权

US6084808A Circuits and methods for burn-in of integrated circuits using potential differences between adjacent main word lines 有权
标题翻译：使用相邻主字线之间的潜在差异来集成电路老化的电路和方法
公开(公告)号：US6084808A
公开(公告)日：2000-07-04
申请号：US199903
申请日：1998-11-25
申请人： Jong-Hyoung Lim , Sang-Seok Kang , Jin-Seok Lee , Byung-Il Ryu
发明人： Jong-Hyoung Lim , Sang-Seok Kang , Jin-Seok Lee , Byung-Il Ryu
IPC分类号： G01R31/26 , G11C29/00 , G11C29/02 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50
摘要： External address signals are applied to an integrated circuit in a burn-in test mode. The external address signals control the voltage levels of adjacent main word lines in a memory array in the integrated circuit. The adjacent main word lines may thereby be configured in to be in opposing logic states. The opposing logic states may provide a potential difference between the adjacent main word lines, thereby increasing the likelihood of detecting microbridges between the adjacent main word lines formed during fabrication of the integrated circuit. The reliability of the integrated circuit may thereby be improved.
摘要翻译：外部地址信号以老化测试模式应用于集成电路。外部地址信号控制集成电路中的存储器阵列中的相邻主字线的电压电平。因此，相邻的主字线可以被配置为处于相反的逻辑状态。相对的逻辑状态可以提供相邻主字线之间的电位差，从而增加在集成电路制造期间形成的相邻主字线之间检测微桥的可能性。可以提高集成电路的可靠性。

4. 发明申请

US20090044063A1 Semiconductor memory device and test system of a semiconductor memory device 审中-公开
标题翻译：一种半导体存储器件的半导体存储器件和测试系统
公开(公告)号：US20090044063A1
公开(公告)日：2009-02-12
申请号：US11974342
申请日：2007-10-12
申请人： Yong-Hwan Cho , Byung-Heon Kwak , Hyun-Soon Jang , Jae-Hoon Joo , Seung-Whan Seo , Jong-Hyoung Lim
发明人： Yong-Hwan Cho , Byung-Heon Kwak , Hyun-Soon Jang , Jae-Hoon Joo , Seung-Whan Seo , Jong-Hyoung Lim
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G11C29/56 , G11C29/56008 , G11C2029/2602 , G11C2029/5602
摘要： A semiconductor memory device includes a memory core unit, N data output buffers, N data output ports, and a plurality of test logic circuits. The memory core unit stores test data through N data lines. The N data output buffers are respectively connected to the corresponding N data lines. The N data output ports are connected to the corresponding N data output buffers, and exchange the test data with an external tester respectively. The plurality of test logic circuits receives the test data through the K data lines from the N data lines, performs test logic operation on the received test data, and provides a data output buffer control signal that determines activation of K data output buffers of the N data output buffers in test mode. The semiconductor memory device reduces test cycle.
摘要翻译：半导体存储器件包括存储器核心单元，N个数据输出缓冲器，N个数据输出端口以及多个测试逻辑电路。存储核心单元通过N条数据线存储测试数据。 N个数据输出缓冲器分别连接到相应的N个数据线。 N个数据输出端口连接到相应的N个数据输出缓冲器，并分别与外部测试仪交换测试数据。多个测试逻辑电路通过来自N条数据线的K条数据线接收测试数据，对所接收的测试数据进行测试逻辑运算，并提供一个数据输出缓冲器控制信号，该信号确定N个数据输出缓冲器的激活测试模式下的数据输出缓冲区。半导体存储器件降低了测试周期。

5. 发明授权

US08015459B2 Semiconductor memory device and method of performing a memory operation 有权
标题翻译：半导体存储器件和执行存储器操作的方法
公开(公告)号：US08015459B2
公开(公告)日：2011-09-06
申请号：US12654644
申请日：2009-12-28
申请人： Jong-Hyoung Lim , Sang-Seok Kang
发明人： Jong-Hyoung Lim , Sang-Seok Kang
IPC分类号： G11C29/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1096 , G11C11/4096
摘要： A semiconductor memory device and method directed to performing a memory operation in a semiconductor memory device are provided. The method includes receiving a write command signal from a memory controller; receiving data from the memory controller, the data including n pieces of data, wherein the k-th piece of data comprises masking data to be masked; and receiving a data masking signal from the memory controller, the data masking signal including enable information that enables data masking, and non-enable information for not enabling data masking, wherein the enable information is used to mask the k-th piece of data. A latency between receiving the write command signal and receiving the enable information is less than a latency between receiving the write command and receiving the k-th piece of data.
摘要翻译：提供一种半导体存储器件和方法，用于在半导体存储器件中执行存储器操作。该方法包括从存储器控制器接收写命令信号; 从所述存储器控制器接收数据，所述数据包括n条数据，其中所述第k条数据包括要屏蔽的掩蔽数据; 以及从所述存储器控制器接收数据屏蔽信号，所述数据屏蔽信号包括启用数据屏蔽的使能信息，以及不启用数据屏蔽的非使能信息，其中所述使能信息用于掩蔽所述第k条数据。接收写命令信号和接收使能信息之间的等待时间小于接收写命令和接收第k条数据之间的等待时间。

6. 发明授权

US07391254B2 Circuit and method of generating internal supply voltage in semiconductor memory device 有权
标题翻译：在半导体存储器件中产生内部电源电压的电路和方法
公开(公告)号：US07391254B2
公开(公告)日：2008-06-24
申请号：US11521178
申请日：2006-09-14
申请人： Jong-Hyoung Lim , Sang-Seok Kang , Sang-Man Byun
发明人： Jong-Hyoung Lim , Sang-Seok Kang , Sang-Man Byun
IPC分类号： G05F1/10
CPC分类号： G11C5/147 , G11C11/4074
摘要： An internal supply voltage generation circuit includes first and second driving circuits and a resistive device. The first driving circuit receives a feedback voltage from a first node and generates a first output voltage based on first and second reference voltages to provide the first output voltage to the first node. The first output voltage is maintained between the first and second reference voltages. The second driving circuit receives a feedback voltage from a second node voltage and generates a second output voltage based on third and fourth reference voltages to provide the second output voltage to the second node. The second output voltage is maintained between the third and fourth reference voltages, and the second output voltage of the second node is provided as an internal supply voltage. The resistive device is coupled between the first and second nodes.
摘要翻译：内部电源电压产生电路包括第一和第二驱动电路和电阻装置。第一驱动电路从第一节点接收反馈电压，并且基于第一和第二参考电压产生第一输出电压，以向第一节点提供第一输出电压。第一输出电压保持在第一和第二参考电压之间。第二驱动电路从第二节点电压接收反馈电压，并且基于第三和第四参考电压产生第二输出电压，以向第二节点提供第二输出电压。第二输出电压保持在第三和第四参考电压之间，第二节点的第二输出电压被提供为内部电源电压。电阻设备耦合在第一和第二节点之间。

7. 发明授权

US07675316B2 Semiconductor memory device including on die termination circuit and on die termination method thereof 失效
标题翻译：半导体存储器件包括管芯端接电路及其管芯端接方法
公开(公告)号：US07675316B2
公开(公告)日：2010-03-09
申请号：US11429365
申请日：2006-05-05
申请人： Jong-Hyoung Lim , Sang-Seok Kang
发明人： Jong-Hyoung Lim , Sang-Seok Kang
IPC分类号： H03K17/16
CPC分类号： G11C7/1078 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084
摘要： A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.
摘要翻译：提供半导体存储器件。该器件包括通过检测通过焊盘输入的信号的相位变化来控制终端电阻值的芯片上终端电路。此外，当在时钟信号的n（n为正整数）周期期间输入相同的相位信号时，导线端接电路改变终端电阻值。

8. 发明申请

US20080052567A1 Semiconductor memory device and method thereof 有权
标题翻译：半导体存储器件及其方法
公开(公告)号：US20080052567A1
公开(公告)日：2008-02-28
申请号：US11730273
申请日：2007-03-30
申请人： Jong-Hyoung Lim , Sang-Seok Kang
发明人： Jong-Hyoung Lim , Sang-Seok Kang
IPC分类号： G11C29/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1096 , G11C11/4096
摘要： A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.
摘要翻译：提供一种半导体存储器件及其方法。示例性方法可以涉及在半导体存储器件中执行存储器操作，并且可以包括接收对应于所接收的数据的至少一部分的数据和数据屏蔽信号，响应于写入命令和数据屏蔽信号，被配置为阻止所接收的数据的至少一部分被写入到存储器中，并且针对每个接收的数据和数据屏蔽信号配置不同的定时参数，从而执行写入命令而没有将所接收的数据的至少一部分写入存储器。

9. 发明授权

US07466616B2 Bit line sense amplifier and method thereof 有权
标题翻译：位线读出放大器及其方法
公开(公告)号：US07466616B2
公开(公告)日：2008-12-16
申请号：US11498721
申请日：2006-08-04
申请人： Sang-Man Byun , Sang-Seok Kang , Jong-Hyoung Lim
发明人： Sang-Man Byun , Sang-Seok Kang , Jong-Hyoung Lim
IPC分类号： G11C7/02
CPC分类号： G11C11/4091 , G11C7/08
摘要： A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage difference between the first bit line and the second bit line. The example bit line sense amplifier may further include a power supply voltage providing circuit configured to provide a first power supply voltage and a second power supply voltage to the sense amplifying circuit in response to first and second bit line sensing control signals. The bit line sense amplifier may further include a bit line voltage compensation circuit configured to prevent a voltage-reduction at the first bit line and the second bit line for a delay period, the delay period including at least a period of time after a pre-charging of the first and second bit lines, in response to one or more of the first and second bit line sensing control signals.
摘要翻译：提供了位线读出放大器及其方法。示例性位线读出放大器可以包括耦合在第一位线和第二位线之间的读出放大电路。感测放大电路可以被配置为放大第一位线和第二位线之间的电压差。示例性位线读出放大器还可以包括电源电压提供电路，其被配置为响应于第一和第二位线检测控制信号向感测放大电路提供第一电源电压和第二电源电压。位线读出放大器还可以包括位线电压补偿电路，配置为在延迟时段内防止在第一位线和第二位线处的电压降低，该延迟周期至少包括预处理后的一段时间，响应于第一和第二位线感测控制信号中的一个或多个，对第一和第二位线进行充电。

10. 发明申请

US20070058316A1 Semiconductor device having fuse circuits 审中-公开
标题翻译：具有熔丝电路的半导体装置
公开(公告)号：US20070058316A1
公开(公告)日：2007-03-15
申请号：US11495296
申请日：2006-07-28
申请人： Jong-Hyoung Lim , Sang-Seok Kang , Yong-Hwan Jeong , Sang-Man Byun
发明人： Jong-Hyoung Lim , Sang-Seok Kang , Yong-Hwan Jeong , Sang-Man Byun
IPC分类号： H02H5/04
CPC分类号： G11C17/18
摘要： Provided is a semiconductor device including a plurality of fuse circuits. Each of the fuse circuits includes: a first signal generator generating a first signal to a first node in response to a power-up signal; a pull-down transistor pulling down a second node in response to the first signal; a pull-up transistor and a fuse which are connected in series between a power supply voltage and the second node and pulling up the second node in response to the first signal when the fuse is not cut; a buffer buffering a signal output from the second node and generating a control signal; and a standby reset transistor resetting the second node in response to the control signal output from the buffer, wherein the pull-down transistor and the standby reset transistor have threshold voltages lower than a threshold voltage of the buffer. Also, each of the fuse circuits further includes an active reset transistor resetting the second node in the active mode in response to the reset control signal. Accordingly, the semiconductor device can reduce an undesired leakage current when the fuse is not cut, and also prevent change in the state of the control signal when the fuse is cut.
摘要翻译：提供了包括多个熔丝电路的半导体器件。每个熔丝电路包括：响应于上电信号而向第一节点产生第一信号的第一信号发生器; 一个下拉晶体管，响应于第一个信号而拉下第二个节点; 一个上拉晶体管和一个保险丝，它们在电源电压和第二个节点之间串联连接，并且当保险丝不被切断时，响应于第一个信号提升第二个节点; 缓冲从第二节点输出的信号并产生控制信号的缓冲器; 以及备用复位晶体管，其响应于从所述缓冲器输出的控制信号而重置所述第二节点，其中所述下拉晶体管和所述待机复位晶体管具有低于所述缓冲器的阈值电压的阈值电压。此外，每个熔丝电路还包括有效复位晶体管，以响应于复位控制信号在激活模式下复位第二节点。因此，当保险丝不被切断时，半导体器件可以减少不期望的泄漏电流，并且还可以防止当熔丝被切断时控制信号的状态的变化。

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