专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06774455B2 Semiconductor device with a collector contact in a depressed well-region 有权
标题翻译：半导体器件在凹陷阱区域具有集电极接触
公开(公告)号：US06774455B2
公开(公告)日：2004-08-10
申请号：US10262206
申请日：2002-09-30
申请人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
发明人： Jeffrey A. Babcock , Christoph Dirnecker , Angelo Pinto , Scott G. Balster , Michael Schober , Alfred Haeusler
IPC分类号： H01L29737
CPC分类号： H01L29/66265 , H01L29/41708 , H01L29/66272 , H01L29/7317 , H01L29/732
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. At least part of the active region is removed to form a shallow trench opening. A dielectric layer is formed proximate the active region at least partially within the shallow trench opening. At least part of the dielectric layer is removed to form a collector contact region. A collector contact may be formed at the collector contact region. The collector contact may be operable to electrically contact the buried layer.
摘要翻译：半导体器件的制造方法包括形成半导体衬底的掩埋层。在掩埋层的至少一部分附近形成有源区。移除活性区域的至少一部分以形成浅沟槽开口。在浅沟槽开口内至少部分地在有源区域附近形成电介质层。去除介电层的至少一部分以形成集电极接触区域。集电极触点可以在集电极接触区域形成。集电极触点可操作以电接触埋层。

2. 发明授权

US06646323B2 Zero mask high density metal/insulator/metal capacitor 有权
公开(公告)号：US06646323B2
公开(公告)日：2003-11-11
申请号：US09849730
申请日：2001-05-04
申请人： Christoph Dirnecker , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Angelo Pinto
发明人： Christoph Dirnecker , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Angelo Pinto
IPC分类号： H01L2900
CPC分类号： H01L28/40 , H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor. The resulting capacitor has a relatively large effective electrode surface area (which is a function of the depth of the via) for a given lateral dimension.

3. 发明授权

US07164186B2 Structure of semiconductor device with sinker contact region 有权
标题翻译：具有沉降片接触区域的半导体器件的结构
公开(公告)号：US07164186B2
公开(公告)日：2007-01-16
申请号：US10939221
申请日：2004-09-10
申请人： Angelo Pinto , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Christoph Dirnecker
发明人： Angelo Pinto , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Christoph Dirnecker
IPC分类号： H01L29/70
CPC分类号： H01L29/66272 , H01L29/41708
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
摘要翻译：半导体器件的制造方法包括形成半导体衬底的掩埋层。在掩埋层的至少一部分附近形成有源区。在掩埋层的至少一部分附近形成第一隔离结构。在活性区域的至少一部分附近形成第二隔离结构。在活性区域的至少一部分附近形成基底层。在基底层的至少一部分附近形成电介质层，然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。发射极结构形成在发射极接触位置。形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。沉降片接触区域具有第一深度。该方法还可以包括形成栅极结构。形成栅极结构包括蚀刻沉降片接触区域，从而将沉降片接触区域的第一深度增加到第二深度。

4. 发明授权

US06391707B1 Method of manufacturing a zero mask high density metal/insulator/metal capacitor 有权
标题翻译：制造零掩模高密度金属/绝缘体/金属电容器的方法
公开(公告)号：US06391707B1
公开(公告)日：2002-05-21
申请号：US09849299
申请日：2001-05-04
申请人： Christoph Dirnecker , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Angelo Pinto
发明人： Christoph Dirnecker , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Angelo Pinto
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/3212 , H01L23/5223 , H01L28/90 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to a structure and method of forming an integrated circuit MIM capacitor having a relatively capacitance without the need for an additional mask step. Methods of forming integrated circuit capacitors include the steps of forming a standard via and one or more enlarged vias in an electrically insulating layer during the same patterning process and then forming an electrically conductive first electrode layer which fills the standard via and overlays the enlarged vias in a conformal manner. A dielectric layer is then formed over the electrically conductive first electrode layer. Next, an electrically conductive second electrode layer is formed over the dielectric layer, which overlays and/or fills the enlarged vias. A step is then performed to planarize the second electrode layer, the dielectric layer, and the first electrode layer to define the electrodes of a capacitor. The resulting capacitor has a relatively large effective electrode surface area (which is a function of the depth of the via) for a given lateral dimension.
摘要翻译：本发明涉及形成具有相对电容的集成电路MIM电容器的结构和方法，而不需要额外的掩模步骤。形成集成电路电容器的方法包括以下步骤：在相同的图案化工艺期间在电绝缘层中形成标准通孔和一个或多个放大通孔，然后形成填充标准通孔的导电第一电极层并覆盖放大的通孔保形方式。然后在导电的第一电极层上形成电介质层。接下来，在电介质层上形成导电的第二电极层，覆盖和/或填充放大的通孔。然后执行步骤以使第二电极层，电介质层和第一电极层平坦化，以限定电容器的电极。对于给定的横向尺寸，所得的电容器具有相对较大的有效电极表面积（其是通孔的深度的函数）。

5. 发明授权

US06806159B2 Method for manufacturing a semiconductor device with sinker contact region 有权
标题翻译：制造具有沉降片接触区域的半导体器件的方法
公开(公告)号：US06806159B2
公开(公告)日：2004-10-19
申请号：US10262211
申请日：2002-09-30
申请人： Angelo Pinto , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Christoph Dirnecker
发明人： Angelo Pinto , Jeffrey A. Babcock , Michael Schober , Scott G. Balster , Christoph Dirnecker
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L29/41708
摘要： A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.
摘要翻译：半导体器件的制造方法包括形成半导体衬底的掩埋层。在掩埋层的至少一部分附近形成有源区。在掩埋层的至少一部分附近形成第一隔离结构。在活性区域的至少一部分附近形成第二隔离结构。在活性区域的至少一部分附近形成基底层。在基底层的至少一部分附近形成电介质层，然后在发射极接触位置和沉降片接触位置移除介电层的至少一部分。发射极结构形成在发射极接触位置。形成发射极结构包括在沉降片接触位置蚀刻半导体器件以形成沉降片接触区域。沉降片接触区域具有第一深度。该方法还可以包括形成栅极结构。形成栅极结构包括蚀刻沉降片接触区域，从而将沉降片接触区域的第一深度增加到第二深度。

6. 发明授权

US08247300B2 Control of dopant diffusion from buried layers in bipolar integrated circuits 有权
标题翻译：控制双极集成电路中埋层的掺杂剂扩散
公开(公告)号：US08247300B2
公开(公告)日：2012-08-21
申请号：US12627794
申请日：2009-11-30
申请人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
发明人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
IPC分类号： H01L21/8222
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译：公开了一种集成电路及其制造方法。集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

7. 发明授权

US06838348B2 Integrated process for high voltage and high performance silicon-on-insulator bipolar devices 有权
标题翻译：用于高电压和高性能绝缘体上的双极器件的集成工艺
公开(公告)号：US06838348B2
公开(公告)日：2005-01-04
申请号：US10844144
申请日：2004-05-12
申请人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
发明人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
IPC分类号： H01L21/331 , H01L21/84 , H01L27/082 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/73
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/0826 , H01L27/1203 , H01L29/0692 , H01L29/0821 , H01L29/7317
摘要： High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.
摘要翻译：公开了绝缘体上硅（SOI）集成电路中的高电压双极晶体管（30,60）。在一个公开的实施例中，集电极区域（28）形成在设置在掩埋绝缘体层（22）上的外延硅（24,25）中。基极区域（32）和发射极（36）设置在集电极区域（28）的上方。掩埋集电极区域（31）设置在远离基极区域（32）的外延硅（24）中。晶体管可以以常规方式布置成矩形方式，或者通过形成环形埋层集电极区域（31）来布置。根据另一公开的实施例，高压晶体管（60）包括中心隔离结构（62），使得基极区域（65）和发射极区域（66）是环形的，以提供改进的性能。还公开了与高性能晶体管（40）同时制造高压晶体管（30,60）的工艺。

8. 发明申请

US20100279481A1 CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS 有权
标题翻译：双极性集成电路中碲化镓的掺杂扩散控制
公开(公告)号：US20100279481A1
公开(公告)日：2010-11-04
申请号：US12627794
申请日：2009-11-30
申请人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
发明人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
IPC分类号： H01L21/331
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译：公开了一种集成电路及其制造方法。集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

9. 发明授权

US06770952B2 Integrated process for high voltage and high performance silicon-on-insulator bipolar devices 有权
公开(公告)号：US06770952B2
公开(公告)日：2004-08-03
申请号：US10132817
申请日：2002-04-25
申请人： Jeffrey A. Babcock , Gregory E Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
发明人： Jeffrey A. Babcock , Gregory E Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
IPC分类号： H01L27082
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/0826 , H01L27/1203 , H01L29/0692 , H01L29/0821 , H01L29/7317
摘要： High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.

10. 发明授权

US06407425B1 Programmable neuron MOSFET on SOI 有权
标题翻译： SOI上的可编程神经元MOSFET
公开(公告)号：US06407425B1
公开(公告)日：2002-06-18
申请号：US09952451
申请日：2001-09-14
申请人： Jeffrey A. Babcock , Scott G. Balster , Gregory E. Howard , Angelo Pinto , Philipp Steinmann
发明人： Jeffrey A. Babcock , Scott G. Balster , Gregory E. Howard , Angelo Pinto , Philipp Steinmann
IPC分类号： H01L29788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/1203
摘要： The instant invention describes a programmable neuron MOSFET structure formed on SOI substrates. A number of input capacitor structures (241, 231) are formed on a SOI substrate. The substrate region of the capacitors (330, 340) are completely isolated from each other by isolation structures (270). In addition the transistor structure (210) of the neuron MOSFET is completely isolated from the capacitor structures (241, 231) by the isolation structure (270). The neuron MOSFET also comprises a contiguous floating conductive layer (200, 230, and 240) which forms the gate structure of the capacitors (230, 240) and the floating gate (200) of the transistor structure.
摘要翻译：本发明描述了在SOI衬底上形成的可编程神经元MOSFET结构。多个输入电容器结构（241,231）形成在SOI衬底上。电容器（330,340）的衬底区域通过隔离结构（270）彼此完全隔离。此外，神经元MOSFET的晶体管结构（210）通过隔离结构（270）与电容器结构（241,231）完全隔离。神经元MOSFET还包括形成晶体管结构的电容器（230,240）和浮动栅极（200）的栅极结构的连续的浮动导电层（200,230和240）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式