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1. 发明授权

US06407425B1 Programmable neuron MOSFET on SOI 有权
标题翻译： SOI上的可编程神经元MOSFET
公开(公告)号：US06407425B1
公开(公告)日：2002-06-18
申请号：US09952451
申请日：2001-09-14
申请人： Jeffrey A. Babcock , Scott G. Balster , Gregory E. Howard , Angelo Pinto , Philipp Steinmann
发明人： Jeffrey A. Babcock , Scott G. Balster , Gregory E. Howard , Angelo Pinto , Philipp Steinmann
IPC分类号： H01L29788
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/1203
摘要： The instant invention describes a programmable neuron MOSFET structure formed on SOI substrates. A number of input capacitor structures (241, 231) are formed on a SOI substrate. The substrate region of the capacitors (330, 340) are completely isolated from each other by isolation structures (270). In addition the transistor structure (210) of the neuron MOSFET is completely isolated from the capacitor structures (241, 231) by the isolation structure (270). The neuron MOSFET also comprises a contiguous floating conductive layer (200, 230, and 240) which forms the gate structure of the capacitors (230, 240) and the floating gate (200) of the transistor structure.
摘要翻译：本发明描述了在SOI衬底上形成的可编程神经元MOSFET结构。多个输入电容器结构（241,231）形成在SOI衬底上。电容器（330,340）的衬底区域通过隔离结构（270）彼此完全隔离。此外，神经元MOSFET的晶体管结构（210）通过隔离结构（270）与电容器结构（241,231）完全隔离。神经元MOSFET还包括形成晶体管结构的电容器（230,240）和浮动栅极（200）的栅极结构的连续的浮动导电层（200,230和240）。

2. 发明授权

US08247300B2 Control of dopant diffusion from buried layers in bipolar integrated circuits 有权
标题翻译：控制双极集成电路中埋层的掺杂剂扩散
公开(公告)号：US08247300B2
公开(公告)日：2012-08-21
申请号：US12627794
申请日：2009-11-30
申请人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
发明人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
IPC分类号： H01L21/8222
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译：公开了一种集成电路及其制造方法。集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

3. 发明授权

US06838348B2 Integrated process for high voltage and high performance silicon-on-insulator bipolar devices 有权
标题翻译：用于高电压和高性能绝缘体上的双极器件的集成工艺
公开(公告)号：US06838348B2
公开(公告)日：2005-01-04
申请号：US10844144
申请日：2004-05-12
申请人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
发明人： Jeffrey A. Babcock , Gregory E. Howard , Angelo Pinto , Phillipp Steinmann , Scott G. Balster
IPC分类号： H01L21/331 , H01L21/84 , H01L27/082 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/73
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/0826 , H01L27/1203 , H01L29/0692 , H01L29/0821 , H01L29/7317
摘要： High-voltage bipolar transistors (30, 60) in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region (28) is formed in epitaxial silicon (24, 25) disposed over a buried insulator layer (22). A base region (32) and emitter (36) are disposed over the collector region (28). Buried collector region (31) are disposed in the epitaxial silicon (24) away from the base region (32). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (31). According to another disclosed embodiment, a high voltage transistor (60) includes a central isolation structure (62), so that the base region (65) and emitter region (66) are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor (30, 60) simultaneously with a high performance transistor (40) is also disclosed.
摘要翻译：公开了绝缘体上硅（SOI）集成电路中的高电压双极晶体管（30,60）。在一个公开的实施例中，集电极区域（28）形成在设置在掩埋绝缘体层（22）上的外延硅（24,25）中。基极区域（32）和发射极（36）设置在集电极区域（28）的上方。掩埋集电极区域（31）设置在远离基极区域（32）的外延硅（24）中。晶体管可以以常规方式布置成矩形方式，或者通过形成环形埋层集电极区域（31）来布置。根据另一公开的实施例，高压晶体管（60）包括中心隔离结构（62），使得基极区域（65）和发射极区域（66）是环形的，以提供改进的性能。还公开了与高性能晶体管（40）同时制造高压晶体管（30,60）的工艺。

4. 发明申请

US20100279481A1 CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS 有权
标题翻译：双极性集成电路中碲化镓的掺杂扩散控制
公开(公告)号：US20100279481A1
公开(公告)日：2010-11-04
申请号：US12627794
申请日：2009-11-30
申请人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
发明人： Jeffrey A. Babcock , Angelo Pinto , Manfred Schiekofer , Scott G. Balster , Gregory E. Howard , Alfred Hausler
IPC分类号： H01L21/331
CPC分类号： H01L29/66265 , H01L21/82285 , H01L29/66242 , H01L29/7317 , H01L29/7378
摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.
摘要翻译：公开了一种集成电路及其制造方法。集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

5. 发明授权

US07422972B2 On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits 有权
标题翻译：片上加热用于多晶硅和多晶硅 - 锗 - 锗电阻器的电气修整和用于集成电路的电可编程保险丝
公开(公告)号：US07422972B2
公开(公告)日：2008-09-09
申请号：US11182981
申请日：2005-07-15
申请人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
发明人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
IPC分类号： H01L21/44
CPC分类号： H01L21/76886 , H01L21/76888 , H01L23/345 , H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.
摘要翻译：形成用于使用微调电阻器和/或可编程保险丝的集成电路可编程结构（60）。可编程结构包括将加热元件（70）放置在可编程结构（60）附近以在编程期间加热可编程结构（60）。

6. 发明授权

US06958523B2 On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits 有权
标题翻译：片上加热用于多晶硅和多晶硅 - 锗 - 锗电阻器的电气修整和用于集成电路的电可编程保险丝
公开(公告)号：US06958523B2
公开(公告)日：2005-10-25
申请号：US09949541
申请日：2001-09-07
申请人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
发明人： Jeffrey A. Babcock , Angelo Pinto , Gregory E. Howard , Philipp Steinmann , Scott Balster
IPC分类号： H01C7/13 , H01C17/26 , H01L23/34 , H01L27/08 , H01L29/00
CPC分类号： H01L27/0802 , H01C7/13 , H01C17/267 , H01L23/345 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit programmable structure (60) is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements (70) in close proximity to the programmable structure (60) to heat the programmable structure (60) during programming.
摘要翻译：形成用于使用微调电阻器和/或可编程保险丝的集成电路可编程结构（60）。可编程结构包括将加热元件（70）放置在可编程结构（60）附近以在编程期间加热可编程结构（60）。

7. 发明授权

US08703568B2 Advanced CMOS using super steep retrograde wells 有权
标题翻译：先进的CMOS使用超级陡逆流井
公开(公告)号：US08703568B2
公开(公告)日：2014-04-22
申请号：US13359125
申请日：2012-01-26
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

8. 发明授权

US07064399B2 Advanced CMOS using super steep retrograde wells 有权
公开(公告)号：US07064399B2
公开(公告)日：2006-06-20
申请号：US09948856
申请日：2001-09-07
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L31/119
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

9. 发明申请

US20120164802A1 ADVANCED CMOS USING SUPER STEEP RETROGRADE WELLS 有权
标题翻译：高级CMOS使用超级梯形变压器
公开(公告)号：US20120164802A1
公开(公告)日：2012-06-28
申请号：US13359125
申请日：2012-01-26
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

10. 发明授权

US07199430B2 Advanced CMOS using super steep retrograde wells 有权
标题翻译：先进的CMOS使用超级陡逆流井
公开(公告)号：US07199430B2
公开(公告)日：2007-04-03
申请号：US11362908
申请日：2006-02-28
申请人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
发明人： Jeffrey A. Babcock , Angelo Pinto , Scott Balster , Alfred Haeusler , Gregory E. Howard
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66659 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L21/823892 , H01L29/1045 , H01L29/105 , H01L29/1083 , H01L29/36 , H01L29/78612 , H01L29/78654
摘要： The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).
摘要翻译：本发明是一种用于在MOS晶体管结构中形成超陡掺杂分布的方法。该方法包括在栅极电介质（50）下面形成含碳层（110），并在MOS晶体管的源极和漏极区域（80）形成。含碳层（110）将防止掺杂剂扩散到栅极电介质层（50）正下方的区域（40）中。

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