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1. 发明授权

US06395633B1 Method of forming micro-via 有权
标题翻译：形成微孔的方法
公开(公告)号：US06395633B1
公开(公告)日：2002-05-28
申请号：US09871206
申请日：2001-05-31
申请人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chin-Chung Chang
发明人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chin-Chung Chang
IPC分类号： H01L2144
CPC分类号： H05K3/4647 , H05K3/108 , H05K3/243 , H05K2203/0542 , H05K2203/0733
摘要： A method of forming a micro-via, for fabrication and design of a layout of a circuit board. A patterned conductive wiring layer is formed on the substrate. A copper layer is plated onto the substrate and the conductive wiring layer. A photoresist layer is formed on the copper layer. A part of the photoresist layer is removed to expose a part of the copper layer. Using the copper layer as a seed layer, a conductive pillar is formed on the exposed part of the copper layer. The photoresist layer is removed. The exposed plated copper layer is removed. An insulation layer is formed on surfaces of the substrate and the conductive pillar. A part of the insulation layer is removed to expose the conductive pillar. A patterned conductive wiring layer is formed on the conductive pillar.
摘要翻译：一种形成微通孔的方法，用于制造和设计电路板的布局。在基板上形成有图案的导电布线层。将铜层镀在基板和导电布线层上。在铜层上形成光致抗蚀剂层。去除光致抗蚀剂层的一部分以露出铜层的一部分。使用铜层作为种子层，在铜层的露出部分上形成导电柱。去除光致抗蚀剂层。暴露的镀铜层被去除。在基板和导电柱的表面上形成绝缘层。去除绝缘层的一部分以露出导电柱。在导电柱上形成有图案的导电布线层。

2. 发明授权

US06749737B2 Method of fabricating inter-layer solid conductive rods 有权
标题翻译：制造层间固体导电棒的方法
公开(公告)号：US06749737B2
公开(公告)日：2004-06-15
申请号：US09927723
申请日：2001-08-10
申请人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chih-Hao Yeh
发明人： Jao-Chin Cheng , Chang-Chin Hsieh , Chih-Peng Fan , Chih-Hao Yeh
IPC分类号： C25D502
CPC分类号： H05K3/423 , C25D1/003 , H05K3/0035 , H05K3/4602 , H05K2201/0355 , H05K2201/0394 , H05K2203/025 , H05K2203/0554 , H05K2203/0733
摘要： A method of forming a solid inter-layer conductive rod. A printed circuit board comprising an insulating core layer, a first conductive layer and a second conductive layer is provided. The insulating core layer is sandwiched between the first conductive layer and the second conductive layer. A first opening that exposes a portion of the insulating core layer is formed in the first conductive layer. The exposed insulating core layer is removed by laser drilling to form a second opening that exposes a portion of the second conductive layer. An electroplating process is conducted using the second conductive layer as a negative electrode so that conductive material solidly fills the first opening and the second opening to form a solid conductive rod.
摘要翻译：形成固体层间导电棒的方法。提供了包括绝缘芯层，第一导电层和第二导电层的印刷电路板。绝缘芯层夹在第一导电层和第二导电层之间。在第一导电层中形成露出绝缘芯层的一部分的第一开口。暴露的绝缘芯层通过激光钻孔去除以形成露出第二导电层的一部分的第二开口。使用第二导电层作为负极进行电镀工艺，使得导电材料牢固地填充第一开口和第二开口以形成固体导电棒。

3. 发明授权

US06709897B2 Method of forming IC package having upward-facing chip cavity 有权
标题翻译：形成具有向上的芯片腔的IC封装的方法
公开(公告)号：US06709897B2
公开(公告)日：2004-03-23
申请号：US10050074
申请日：2002-01-15
申请人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
发明人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H01L23/49822 , H01L23/13 , H01L23/142 , H01L24/24 , H01L24/82 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05024 , H01L2224/05548 , H01L2224/05569 , H01L2224/12105 , H01L2224/24246 , H01L2224/24247 , H01L2224/32245 , H01L2224/45144 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/92244 , H01L2924/01075 , H01L2924/01079 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2224/24227 , H01L2924/00
摘要： A method of forming an integrated circuit package with an upward-facing chip cavity such that the fabrication of the substrate and the packaging of silicon chip are combined. By forming a patterned dielectric layer to expose bonding pads on a silicon chip and subsequently connecting the bonding pad on the chip with trace lines on the substrate through electroplating, reliable connections between the chip and substrate are formed and no more bubbles are formed inside the dielectric layer.
摘要翻译：一种形成具有朝上的芯片空腔的集成电路封装的方法，使得基板的制造和硅芯片的封装被组合。通过形成图案化的电介质层以暴露硅芯片上的焊盘，随后通过电镀将衬底上的接合焊盘与衬底上的迹线连接，形成芯片和衬底之间的可靠连接，并且在电介质内不再形成气泡层。

4. 发明授权

US06506632B1 Method of forming IC package having downward-facing chip cavity 有权
标题翻译：形成具有向下的芯片腔的IC封装的方法
公开(公告)号：US06506632B1
公开(公告)日：2003-01-14
申请号：US10078211
申请日：2002-02-15
申请人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
发明人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H01L24/82 , H01L21/568 , H01L21/6835 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/97 , H01L2224/45144 , H01L2224/73267 , H01L2224/82005 , H01L2224/82039 , H01L2224/82047 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2924/00
摘要： A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating. The adhesive tape is removed. The metallic layer and the conductive layer are patterned. A patterned solder resistant layer is formed over the metallic layer and the conductive layer. The patterned solder resistant layer has a plurality of openings that expose a portion of the conductive layer. A solder ball implant is conducted to form electrical connection between the solder balls and the conductive layer.
摘要翻译：一种形成具有朝下的芯片腔的集成电路封装的方法。提供了包括绝缘芯层和导电层的衬底。在基板中形成通孔，并且在导电层的表面上附着粘合带。硅芯片附着在第一开口底部的暴露的胶带表面上。芯片具有活性表面和背面。所述芯片还包括在所述有源表面上的多个接合焊盘。芯片的背面附着在胶带上。形成图案化的介电层，填充第一开口并覆盖粘合带，活性表面，接合焊盘和绝缘芯层的一部分。图案化电介质层具有暴露接合焊盘和一些通孔的多个开口。通过电镀在开口的暴露表面和图案化电介质层的上表面上形成金属层。去除胶带。金属层和导电层被图案化。在金属层和导电层之上形成图案化的阻焊层。图案化的阻焊层具有暴露导电层的一部分的多个开口。导电焊球植入物以形成焊球和导电层之间的电连接。

5. 发明授权

US06506633B1 Method of fabricating a multi-chip module package 有权
标题翻译：制造多芯片模块封装的方法
公开(公告)号：US06506633B1
公开(公告)日：2003-01-14
申请号：US10078212
申请日：2002-02-15
申请人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
发明人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H01L25/50 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/45 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/0657 , H01L2221/68377 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/24225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/82001 , H01L2224/82039 , H01L2224/97 , H01L2225/0651 , H01L2225/06524 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/15183 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： A method of fabricating a multi-chip module (MCM) package that can fabricate the substrate and the package simultaneously. The bonding pads of a chip are exposed by forming a patterned dielectric layer, and the bonding pads of the chip are electrically connected to the substrate by utilizing to an electroplating to form a metal layer. The present invention provides a fabircating method that can prevent air bubble produced in the patterned dielectric layer and improve the connection ability between the chip and the substrate.
摘要翻译：一种制造可以同时制造衬底和封装的多芯片模块（MCM）封装的方法。芯片的焊盘通过形成图案化的介电层而被曝光，芯片的焊盘通过利用电镀而与基板电连接以形成金属层。本发明提供一种能够防止在图案化电介质层中产生的气泡并提高芯片与基板之间的连接能力的制造方法。

6. 发明申请

US20100294553A1 PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR 审中-公开
标题翻译：具有嵌入式电容器的封装衬底
公开(公告)号：US20100294553A1
公开(公告)日：2010-11-25
申请号：US12851807
申请日：2010-08-06
申请人： Chih-Peng Fan
发明人： Chih-Peng Fan
IPC分类号： H05K1/16
CPC分类号： H05K1/162 , H05K3/4602 , H05K3/4623 , H05K3/4644 , H05K2201/0355 , H05K2201/09536 , H05K2201/09763
摘要： A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one embedded capacitor, at least one dielectric layer and at least one wiring layer. The core circuit board has at least one metal layer, and the core circuit board has at least one conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the core circuit board and connected to the metal layer. At least one dielectric layer covers the core circuit board, and the dielectric layer has an embedded hole. At least one wiring layer covers the dielectric layer and connected to the embedded hole.
摘要翻译：提供具有嵌入式电容器的封装基板。封装衬底包括芯电路板，至少一个嵌入式电容器，至少一个电介质层和至少一个布线层。核心电路板具有至少一个金属层，并且核心电路板具有连接到金属层的至少一个导电通孔。至少一个嵌入式电容器嵌入在核心电路板中并连接到金属层。至少一个电介质层覆盖核心电路板，电介质层具有嵌入孔。至少一个布线层覆盖电介质层并连接到嵌入孔。

7. 发明申请

US20100013068A1 CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF 有权
标题翻译：芯片包装机及其制造方法
公开(公告)号：US20100013068A1
公开(公告)日：2010-01-21
申请号：US12208843
申请日：2008-09-11
申请人： Han-Pei Huang , Chih-Peng Fan
发明人： Han-Pei Huang , Chih-Peng Fan
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49827 , H01L21/4857 , H01L21/486 , H01L21/6835 , H01L23/4334 , H01L23/49822 , H01L23/5389 , H01L24/16 , H01L2221/68345 , H01L2224/16225 , H01L2224/16235 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/19041 , H01L2924/30105 , H05K1/115 , H05K1/162 , H05K3/4602 , H05K2201/09518 , H05K2201/09809 , H01L2224/0401
摘要： A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad.
摘要翻译：公开了一种芯片封装载体，其包括第一电路层，第二电路层，芯层，第三电路层，第一和第三电路层之间的第一电介质层，第四导电层，至少包括焊球垫，第二和第四电路层之间的第二电介质层和至少一个电容器器件，其中芯层至少具有第一通孔; 所述第三电路层设置在所述第一电路层上方，并且至少包括管芯焊盘; 电容器装置设置在第一通孔中。本发明的电容器件包括覆盖第一通孔的壁的第一柱状电极，设置在第一柱状电极中并具有第一盲孔的圆筒形电容器材料和设置在第一盲孔中的第二柱状电极，芯片垫。

8. 发明申请

US20080121417A1 PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR 审中-公开
标题翻译：具有嵌入式电容器的封装衬底
公开(公告)号：US20080121417A1
公开(公告)日：2008-05-29
申请号：US11623553
申请日：2007-01-16
申请人： Chih-Peng Fan
发明人： Chih-Peng Fan
IPC分类号： H05K1/16
CPC分类号： H05K1/162 , H05K3/4602 , H05K3/4623 , H05K3/4644 , H05K2201/0355 , H05K2201/09536 , H05K2201/09763
摘要： A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. At least one metal layer is disposed on a surface of the first core circuit board and at least one first conductive through hole of the first core circuit board is connected to the metal layer. The embedded capacitor is embedded in the first core circuit board and connected to the metal layer. A wiring layer is disposed on a surface of the second core circuit board and at least one second conductive through hole of the second core circuit board is connected to the wiring layer. The dielectric layer is laminated between the first and the second core circuit boards.
摘要翻译：提供具有嵌入式电容器的封装基板。封装衬底包括第一核心电路板，至少一个嵌入式电容器，第二核心电路板和电介质层。至少一个金属层设置在第一芯电路板的表面上，并且第一芯电路板的至少一个第一导电通孔连接到金属层。嵌入式电容器嵌入第一个核心电路板并连接到金属层。布线层设置在第二芯电路板的表面上，并且第二芯电路板的至少一个第二导电通孔连接到布线层。介电层层叠在第一和第二核心电路板之间。

9. 发明授权

US08289725B2 Package substrate having embedded capacitor 有权
标题翻译：封装衬底具有嵌入式电容器
公开(公告)号：US08289725B2
公开(公告)日：2012-10-16
申请号：US12851795
申请日：2010-08-06
申请人： Chih-Peng Fan
发明人： Chih-Peng Fan
IPC分类号： H05K7/00
CPC分类号： H05K1/162 , H05K3/4602 , H05K3/4623 , H05K3/4644 , H05K2201/0355 , H05K2201/09536 , H05K2201/09763
摘要： A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole.
摘要翻译：提供具有嵌入式电容器的封装基板。封装衬底包括芯电路板，至少一个电介质层，至少一个嵌入式电容器和至少一个金属层。核心电路板具有至少一个布线层，并且核心电路板具有连接到布线层的至少一个导电通孔。至少一个电介质层覆盖布线层，电介质层具有至少一个导电通孔。至少一个嵌入式电容器嵌入电介质层。至少一个金属层覆盖电介质层并连接到嵌入式电容器，其中金属层通过导电通孔连接到布线层。

10. 发明授权

US08186049B2 Method of making a circuit structure 有权
标题翻译：制作电路结构的方法
公开(公告)号：US08186049B2
公开(公告)日：2012-05-29
申请号：US12181556
申请日：2008-07-29
申请人： Chih-Peng Fan , Yen-Ti Chia
发明人： Chih-Peng Fan , Yen-Ti Chia
IPC分类号： H05K3/02
CPC分类号： H05K1/111 , H01L2224/16225 , H05K3/108 , H05K3/243 , H05K3/3452 , H05K3/4007 , H05K2201/0367 , H05K2201/0989 , H05K2201/10674 , H05K2203/0574 , Y02P70/611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.
摘要翻译：电路结构的制造方法如下所述。首先，在载体板上形成基底导电层，在基底导电层上形成具有至少一个露出基底导电层的一部分的沟槽的第一图案化电镀层。然后在沟槽中形成第一图案化导电层，并且形成覆盖第一图案化导电层的一部分和第一图案化电镀层的一部分的第二图案化电镀层。在暴露的第一图案化导电层上形成第二图案化导电层。去除第一和第二图案化电镀层和由第一图案化导电层暴露的基底导电层。然后，形成图案化的焊料掩模以覆盖第一图案化导电层的一部分。

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