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1. 发明申请

US20110076802A1 EMBEDDED CHIP PACKAGE PROCESS 有权
标题翻译：嵌入式芯片封装工艺
公开(公告)号：US20110076802A1
公开(公告)日：2011-03-31
申请号：US12960547
申请日：2010-12-06
申请人： David C. H. Cheng
发明人： David C. H. Cheng
IPC分类号： H01L21/50
CPC分类号： H01L24/24 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/3128 , H01L23/5384 , H01L23/5389 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2224/16225 , H01L2224/24051 , H01L2224/24226 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H05K1/187 , H05K3/20 , H05K3/4602 , H05K2201/0358 , H05K2201/10674
摘要： An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole.
摘要翻译：公开了一种嵌入式芯片封装工艺。提供具有第一图案化电路层的第一基板。提供具有第二图案化电路层的第二基板。形成介电材料层以覆盖第一图案化电路层。执行压缩处理以覆盖电介质材料层上的第二衬底，并且将第二图案化电路层嵌入电介质材料层中。执行固化处理以在执行压缩处理的步骤之后固化电介质材料层。通过电介质材料层的至少一个导电插塞被形成为在执行固化过程的步骤之后将第一图案化电路层电连接到第二图案化电路层。在形成导电通孔的步骤之后，去除第一基板，第二基板和至少导电塞子的一部分。

2. 发明申请

US20090284935A1 STRUCTURE AND MANUFACTURING PROCESS FOR CIRCUIT BOARD 有权
标题翻译：电路板结构与制造工艺
公开(公告)号：US20090284935A1
公开(公告)日：2009-11-19
申请号：US12345386
申请日：2008-12-29
申请人： Tsung-Yuan Chen , Shu-Sheng Chiang , David C. H. Cheng
发明人： Tsung-Yuan Chen , Shu-Sheng Chiang , David C. H. Cheng
IPC分类号： H05K3/10 , H05K1/00
CPC分类号： H05K1/02 , H05K1/0265 , H05K1/0298 , H05K1/115 , H05K3/045 , H05K3/107 , H05K3/426 , H05K3/465 , H05K2201/0352 , H05K2201/09736 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155
摘要： A circuit board structure comprising a composite layer, a fine circuit pattern and a patterned conductive layer is provided. The fine circuit pattern is inlaid in the composite layer, and the patterned conductive layer is disposed on a surface of the composite layer. After fine circuit grooves are formed on the surface of the composite layer, conductive material is filled into the grooves to form the fine circuit pattern inlaid in the composite layer. Since this fine circuit pattern has relatively fine line width and spacing, the circuit board structure has a higher wiring density.
摘要翻译：提供了包括复合层，精细电路图案和图案化导电层的电路板结构。精细电路图案嵌入复合层中，并且图案化导电层设置在复合层的表面上。在复合层的表面上形成精细电路槽之后，将导电材料填充到沟槽中以形成复合层中嵌入的精细电路图案。由于该微细电路图案具有相对较细的线宽和间隔，所以电路板结构具有较高的布线密度。

3. 发明授权

US06638858B2 Hole metal-filling method 失效
标题翻译：孔金属填充法
公开(公告)号：US06638858B2
公开(公告)日：2003-10-28
申请号：US10020700
申请日：2001-10-30
申请人： David C. H. Cheng
发明人： David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H05K3/4046 , H01L21/4853 , H05K2201/0347 , H05K2201/0355 , H05K2201/0382 , H05K2201/10234
摘要： A hole metal-filling method, applied to hole filling and electroplating a printed circuit board which has been mechanical-drilled with holes. A plurality of holes is drilled in a substrate. The substrate is placed on a platform. A plurality of metal balls is disposed on a surface of the substrate. By vibrating the platform, a part of the metal balls roll into the holes, while the metal balls not rolling into the holes are removed. The substrate is then placed on a press down unit. The metal balls in the holes are pressed to level with surfaces of the substrate. The substrate is directly electroplated for forming a plating layer closely dovetail to the metal balls.
摘要翻译：孔金属填充方法，适用于已经机械钻孔的印刷电路板的孔填充和电镀。在基板上钻出多个孔。将基板放置在平台上。多个金属球设置在基板的表面上。通过振动平台，金属球的一部分滚动到孔中，而不会滚动到孔中的金属球被去除。然后将基板放置在压下单元上。孔中的金属球被压制以与基底的表面平齐。将基板直接电镀以形成与金属球紧密接合的镀层。

4. 发明授权

US06506632B1 Method of forming IC package having downward-facing chip cavity 有权
标题翻译：形成具有向下的芯片腔的IC封装的方法
公开(公告)号：US06506632B1
公开(公告)日：2003-01-14
申请号：US10078211
申请日：2002-02-15
申请人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
发明人： Jao-Chin Cheng , Chih-Peng Fan , David C. H. Cheng
IPC分类号： H01L2144
CPC分类号： H01L24/82 , H01L21/568 , H01L21/6835 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L24/97 , H01L2224/45144 , H01L2224/73267 , H01L2224/82005 , H01L2224/82039 , H01L2224/82047 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2924/00
摘要： A method of forming an integrated circuit package with a downward-facing chip cavity. A substrate comprising an insulating core layer and a conductive layer is provided. A through-hole is formed in the substrate and an adhesive tape is attached to the surface of the conductive layer. A silicon chip is attached to the exposed adhesive tape surface at the bottom of the first opening. The chip has an active surface and a back surface. The chip further includes a plurality of bonding pads on the active surface. The back surface of the chip is attached to the adhesive tape. A patterned dielectric layer is formed filling the first opening and covering a portion of the adhesive tape, the active surface, the bonding pad and the insulating core layer. The patterned dielectric layer has a plurality of openings that exposes the bonding pads and some through holes. A metallic layer is formed over the exposed surface of the openings and the upper surface of the patterned dielectric layer by electroplating. The adhesive tape is removed. The metallic layer and the conductive layer are patterned. A patterned solder resistant layer is formed over the metallic layer and the conductive layer. The patterned solder resistant layer has a plurality of openings that expose a portion of the conductive layer. A solder ball implant is conducted to form electrical connection between the solder balls and the conductive layer.
摘要翻译：一种形成具有朝下的芯片腔的集成电路封装的方法。提供了包括绝缘芯层和导电层的衬底。在基板中形成通孔，并且在导电层的表面上附着粘合带。硅芯片附着在第一开口底部的暴露的胶带表面上。芯片具有活性表面和背面。所述芯片还包括在所述有源表面上的多个接合焊盘。芯片的背面附着在胶带上。形成图案化的介电层，填充第一开口并覆盖粘合带，活性表面，接合焊盘和绝缘芯层的一部分。图案化电介质层具有暴露接合焊盘和一些通孔的多个开口。通过电镀在开口的暴露表面和图案化电介质层的上表面上形成金属层。去除胶带。金属层和导电层被图案化。在金属层和导电层之上形成图案化的阻焊层。图案化的阻焊层具有暴露导电层的一部分的多个开口。导电焊球植入物以形成焊球和导电层之间的电连接。

5. 发明授权

US08153472B2 Embedded chip package process 有权
标题翻译：嵌入式芯片封装过程
公开(公告)号：US08153472B2
公开(公告)日：2012-04-10
申请号：US12960547
申请日：2010-12-06
申请人： David C. H. Cheng
发明人： David C. H. Cheng
IPC分类号： H01L21/50
CPC分类号： H01L24/24 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/3128 , H01L23/5384 , H01L23/5389 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2221/68359 , H01L2224/16225 , H01L2224/24051 , H01L2224/24226 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H05K1/187 , H05K3/20 , H05K3/4602 , H05K2201/0358 , H05K2201/10674
摘要： An embedded chip package process is disclosed. A first substrate having a first patterned circuit layer is provided. A second substrate having a second patterned circuit layer is provided. A dielectric material layer is formed to cover the first patterned circuit layer. A compression process is performed to cover the second substrate over the dielectric material layer and the second patterned circuit layer is embed into the dielectric material layer. A curing process is performed to cure the dielectric material layer after the step of performing the compression process. At least a conductive plug through the dielectric material layer is formed to electrically connect the first patterned circuit layer to the second patterned circuit layer after the step of performing the curing process. The first substrate, the second substrate and a portion of the at least a conductive plug are removed after the step of forming the conductive through hole.
摘要翻译：公开了一种嵌入式芯片封装工艺。提供具有第一图案化电路层的第一基板。提供具有第二图案化电路层的第二基板。形成介电材料层以覆盖第一图案化电路层。执行压缩处理以覆盖电介质材料层上的第二衬底，并且将第二图案化电路层嵌入电介质材料层中。执行固化处理以在执行压缩处理的步骤之后固化电介质材料层。通过电介质材料层的至少一个导电插塞被形成为在执行固化过程的步骤之后将第一图案化电路层电连接到第二图案化电路层。在形成导电通孔的步骤之后，去除第一基板，第二基板和至少导电塞子的一部分。

6. 发明授权

US07663249B2 Embedded chip package structure 有权
标题翻译：嵌入式芯片封装结构
公开(公告)号：US07663249B2
公开(公告)日：2010-02-16
申请号：US11467168
申请日：2006-08-25
申请人： David C. H. Cheng
发明人： David C. H. Cheng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5389 , H01L23/5384 , H01L24/24 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/24051 , H01L2224/24226 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H05K1/187 , H05K3/20 , H05K3/4602 , H05K2201/0358 , H05K2201/10674
摘要： An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.
摘要翻译：公开了一种嵌入式芯片封装工艺。首先，提供其上具有第一图案化电路层的第一基板。然后，第一芯片设置在第一图案化电路层上并电连接到第一图案化电路层。提供其上具有第二图案化电路层的第二基板。第二芯片设置在第二图案化电路层上并电连接到第二图案化电路层。之后，形成介电材料层并覆盖第一芯片和第一图案化电路层。然后，执行压缩处理以覆盖电介质材料层上的第二衬底，使得第二图案化电路层和第二衬底上的第二芯片被嵌入电介质材料层中。

7. 发明申请

US20090273907A1 CIRCUIT BOARD AND PROCESS THEREOF 审中-公开
标题翻译：电路板及其过程
公开(公告)号：US20090273907A1
公开(公告)日：2009-11-05
申请号：US12112226
申请日：2008-04-30
申请人： Tsung-Yuan Chen , Tzyy-Jang Tseng , Shu-Sheng Chiang , David C. H. Cheng
发明人： Tsung-Yuan Chen , Tzyy-Jang Tseng , Shu-Sheng Chiang , David C. H. Cheng
IPC分类号： H05K3/06 , H05K1/02
CPC分类号： H05K1/0219 , H05K3/107 , H05K3/108 , H05K3/125 , H05K3/243 , H05K3/245 , H05K2201/09236 , H05K2201/09736 , H05K2203/013 , H05K2203/058 , H05K2203/1476 , Y10T29/49155
摘要： A circuit board and process thereof are provided. The circuit board includes a dielectric layer, an active circuit, and two shielding circuits. The dielectric layer has an active surface. The active circuit is disposed on the active surface, and the shielding circuits are respectively disposed on two sides of the active circuit. The height of the shielding circuits is larger than the height of the active circuit.
摘要翻译：提供电路板及其工艺。电路板包括电介质层，有源电路和两个屏蔽电路。电介质层具有活性表面。有源电路设置在有源表面上，屏蔽电路分别设置在有源电路的两侧。屏蔽电路的高度大于有源电路的高度。

8. 发明申请

US20090144972A1 CIRCUIT BOARD AND PROCESS FOR FABRICATING THE SAME 审中-公开
标题翻译：电路板及其制造方法
公开(公告)号：US20090144972A1
公开(公告)日：2009-06-11
申请号：US12047936
申请日：2008-03-13
申请人： David C. H. Cheng , Shao-Chien Lee , Tzyy-Jang Tseng
发明人： David C. H. Cheng , Shao-Chien Lee , Tzyy-Jang Tseng
IPC分类号： H05K3/02
CPC分类号： H05K3/4007 , H05K3/06 , H05K3/062 , H05K3/107 , H05K3/3452 , H05K2201/0341 , H05K2201/0367 , H05K2201/0376 , H05K2201/099 , H05K2203/0384 , H05K2203/0542 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156
摘要： A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.
摘要翻译：提供一种制造电路板的工艺。在该过程中，首先，提供包括绝缘层和至少与绝缘层接触的焊盘的电路基板。接下来，在电路基板上形成阻挡材料层。阻挡材料层完全覆盖绝缘层和垫。然后，在阻挡材料层上形成至少一个导电凸块。导电凸块与焊盘相对，并且阻挡材料层的材料与导电凸块的材料不同。接下来，通过使用导电凸块作为掩模来去除阻挡材料层的一部分，以暴露绝缘层的表面并形成连接在导电凸块和焊盘之间的阻挡层。

9. 发明申请

US20090023246A1 EMBEDDED CHIP PACKAGE PROCESS 有权
标题翻译：嵌入式芯片封装工艺
公开(公告)号：US20090023246A1
公开(公告)日：2009-01-22
申请号：US12234702
申请日：2008-09-21
申请人： David C. H. Cheng
发明人： David C. H. Cheng
IPC分类号： H01L21/50
CPC分类号： H01L23/5389 , H01L23/5384 , H01L24/24 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2224/24051 , H01L2224/24226 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H05K1/187 , H05K3/20 , H05K3/4602 , H05K2201/0358 , H05K2201/10674
摘要： An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.
摘要翻译：公开了一种嵌入式芯片封装工艺。首先，提供其上具有第一图案化电路层的第一基板。然后，第一芯片设置在第一图案化电路层上并电连接到第一图案化电路层。提供其上具有第二图案化电路层的第二基板。第二芯片设置在第二图案化电路层上并电连接到第二图案化电路层。之后，形成介电材料层并覆盖第一芯片和第一图案化电路层。然后，执行压缩处理以覆盖电介质材料层上的第二衬底，使得第二图案化电路层和第二衬底上的第二芯片被嵌入电介质材料层中。

10. 发明申请

US20080036058A1 PACKAGE SUBSTRATE 有权
标题翻译：包装基板
公开(公告)号：US20080036058A1
公开(公告)日：2008-02-14
申请号：US11533765
申请日：2006-09-20
申请人： David C. H. Cheng
发明人： David C. H. Cheng
IPC分类号： H01L23/02
CPC分类号： H01L23/49833 , H01L23/49816 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H05K1/056 , H05K3/4608 , H05K3/4641 , H05K2201/09481 , H05K2201/0949 , H05K2201/09536 , H05K2201/10674 , H01L2224/0401
摘要： A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.
摘要翻译：提供了包括电路板，加强板和至少一个导电通道的封装基板。加强板的第一表面设置在电路板上以抵抗电路板的翘曲。加强板具有对应于暴露在其上的电路板的第一接触件的开口。此外，导电通道的一端位于开口中并电连接到第一触点，导电通道的另一端位于加强板的第二表面上以形成接合焊盘。

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