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1. 发明授权

US08186049B2 Method of making a circuit structure 有权
标题翻译：制作电路结构的方法
公开(公告)号：US08186049B2
公开(公告)日：2012-05-29
申请号：US12181556
申请日：2008-07-29
申请人： Chih-Peng Fan , Yen-Ti Chia
发明人： Chih-Peng Fan , Yen-Ti Chia
IPC分类号： H05K3/02
CPC分类号： H05K1/111 , H01L2224/16225 , H05K3/108 , H05K3/243 , H05K3/3452 , H05K3/4007 , H05K2201/0367 , H05K2201/0989 , H05K2201/10674 , H05K2203/0574 , Y02P70/611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.
摘要翻译：电路结构的制造方法如下所述。首先，在载体板上形成基底导电层，在基底导电层上形成具有至少一个露出基底导电层的一部分的沟槽的第一图案化电镀层。然后在沟槽中形成第一图案化导电层，并且形成覆盖第一图案化导电层的一部分和第一图案化电镀层的一部分的第二图案化电镀层。在暴露的第一图案化导电层上形成第二图案化导电层。去除第一和第二图案化电镀层和由第一图案化导电层暴露的基底导电层。然后，形成图案化的焊料掩模以覆盖第一图案化导电层的一部分。

2. 发明申请

US20120073867A1 CIRCUIT STRUCTURE 审中-公开
标题翻译：电路结构
公开(公告)号：US20120073867A1
公开(公告)日：2012-03-29
申请号：US13313896
申请日：2011-12-07
申请人： Chih-Peng Fan , Yen-Ti Chia
发明人： Chih-Peng Fan , Yen-Ti Chia
IPC分类号： H05K1/09 , H05K1/00
CPC分类号： H05K1/111 , H01L2224/16225 , H05K3/108 , H05K3/243 , H05K3/3452 , H05K3/4007 , H05K2201/0367 , H05K2201/0989 , H05K2201/10674 , H05K2203/0574 , Y02P70/611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A circuit structure suitable for being disposed on a carrier board. The circuit structure comprises a first patterned conductive layer, a second patterned conductive layer, and a solder mask. The first patterned conductive layer is disposed on the carrier board. The second patterned conductive layer is disposed on a part of the first patterned conductive layer. A part of the edge of the second patterned conductive layer and a part of the edge of the first patterned conductive layer are substantially coplanar. The patterned solder mask covers a part of the first patterned conductive layer and has at least one opening for exposing the second patterned conductive layer and a part of the first patterned conductive layer adjacent to the second patterned conductive layer.
摘要翻译：适于布置在载板上的电路结构。电路结构包括第一图案化导电层，第二图案化导电层和焊接掩模。第一图案化导电层设置在载体板上。第二图案化导电层设置在第一图案化导电层的一部分上。第二图案化导电层的边缘的一部分和第一图案化导电层的边缘的一部分基本上共面。图案化的焊接掩模覆盖第一图案化导电层的一部分并且具有用于暴露第二图案化导电层的至少一个开口和与第二图案化导电层相邻的第一图案化导电层的一部分。

3. 发明申请

US20130029500A1 CONNECTOR AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：连接器及其制造方法
公开(公告)号：US20130029500A1
公开(公告)日：2013-01-31
申请号：US13450485
申请日：2012-04-19
申请人： Chih-Peng Fan , Ling-Kai Su , Yen-Ti Chia
发明人： Chih-Peng Fan , Ling-Kai Su , Yen-Ti Chia
IPC分类号： H01R12/71 , H01R43/16
CPC分类号： H01R13/24 , H01R4/04 , H01R43/16 , H01R43/20 , Y10T29/49224
摘要： The present invention provides a connector including a substrate, at least a conductive via disposed inside the substrate, a pad disposed on one surface of the substrate and electrically connected to the conductive via, a resilient flange disposed on the pad, and an anisotropic conductive adhesive interposed between the pad and the resilient flange to electrically connect the pad with the resilient flange.
摘要翻译：本发明提供了一种连接器，其包括基板，至少设置在基板内部的导电通孔，设置在基板的一个表面上并电连接到导电通孔的焊盘，设置在焊盘上的弹性凸缘和各向异性导电粘合剂插入垫和弹性凸缘之间以将垫与弹性凸缘电连接。

4. 发明申请

US20090288858A1 CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：电路结构及其制造方法
公开(公告)号：US20090288858A1
公开(公告)日：2009-11-26
申请号：US12181556
申请日：2008-07-29
申请人： Chih-Peng Fan , Yen-Ti Chia
发明人： Chih-Peng Fan , Yen-Ti Chia
IPC分类号： H05K3/02 , H05K1/00
CPC分类号： H05K1/111 , H01L2224/16225 , H05K3/108 , H05K3/243 , H05K3/3452 , H05K3/4007 , H05K2201/0367 , H05K2201/0989 , H05K2201/10674 , H05K2203/0574 , Y02P70/611 , Y10T29/49126 , Y10T29/4913 , Y10T29/49155 , Y10T29/49165
摘要： A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer.
摘要翻译：电路结构的制造方法如下所述。首先，在载体板上形成基底导电层，在基底导电层上形成具有至少一个露出基底导电层的一部分的沟槽的第一图案化电镀层。然后在沟槽中形成第一图案化导电层，并且形成覆盖第一图案化导电层的一部分和第一图案化电镀层的一部分的第二图案化电镀层。在暴露的第一图案化导电层上形成第二图案化导电层。去除第一和第二图案化电镀层和由第一图案化导电层暴露的基底导电层。然后，形成图案化的焊料掩模以覆盖第一图案化导电层的一部分。

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