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1. 发明授权

US06287924B1 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06287924B1
公开(公告)日：2001-09-11
申请号：US09407213
申请日：1999-09-28
申请人： Chih-Ping Chao , Ih-Chin Chen , Rick L. Wise , Katherine E. Violette , Sreenath Unnikrishnan
发明人： Chih-Ping Chao , Ih-Chin Chen , Rick L. Wise , Katherine E. Violette , Sreenath Unnikrishnan
IPC分类号： H01L21336
CPC分类号： H01L21/28052 , H01L29/665 , H01L29/66545 , H01L29/66628
摘要： Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.
摘要翻译：使用在硅栅极上方延伸的侧壁间隔物，其中间隔物之间的距离超过栅极的长度用于限制栅极的选择性硅生长和随后的自对准硅化物。

2. 发明授权

US06605482B2 Process for monitoring the thickness of layers in a microelectronic device 有权
公开(公告)号：US06605482B2
公开(公告)日：2003-08-12
申请号：US09975637
申请日：2001-10-11
申请人： Francis G. Celii , Maureen A. Hanratty , Katherine E. Violette , Rick L. Wise
发明人： Francis G. Celii , Maureen A. Hanratty , Katherine E. Violette , Rick L. Wise
IPC分类号： H01L2166
CPC分类号： G01N21/55
摘要： A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device. The method additionally includes comparing the at least one optical measurement to the predicted behavior curve and determining the approximate actual depth of the interface in response to the compared optical measurement.

3. 发明授权

US06326281B1 Integrated circuit isolation 有权
标题翻译：集成电路隔离
公开(公告)号：US06326281B1
公开(公告)日：2001-12-04
申请号：US09405278
申请日：1999-09-23
申请人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
发明人： Katherine E. Violette , Rick L. Wise , Stanton P. Ashburn , Mahalingam Nandakumar , Douglas T. Grider
IPC分类号： H01L2136
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/31604 , H01L21/762
摘要： Silicon substrate isolation by epitaxial growth of silicon through windows in a mask made of silicon nitride (202) on silicon oxide (201) with the silicon oxide etched to undercut the silicon nitride; the mask is on a silicon substrate.
摘要翻译：通过在氧化硅（201）上由氮化硅（202）制成的掩模中的硅通过窗口外延生长硅氧化硅衬底，氧化硅被蚀刻以切割氮化硅; 掩模在硅衬底上。

4. 发明授权

US06214736B1 Silicon processing method 有权
标题翻译：硅加工方法
公开(公告)号：US06214736B1
公开(公告)日：2001-04-10
申请号：US09419606
申请日：1999-10-15
申请人： Antonio L. P. Rotondaro , Reima Tapani Laaksonen , Robert Kraft , Charlotte M. Appel , Rebecca J. Gale , Katherine E. Violette
发明人： Antonio L. P. Rotondaro , Reima Tapani Laaksonen , Robert Kraft , Charlotte M. Appel , Rebecca J. Gale , Katherine E. Violette
IPC分类号： H01L2100
CPC分类号： H01L21/3065
摘要： A plasma process is described which produces an undamaged and uncontaminated silicon surface by consuming silicon by continuous oxidation through a surface oxide layer and a simultaneous etch of the exposed silicon oxide surface. The surface silicon dioxide layer thickness is controlled as an equilibrium between oxide growth from oxygen atoms reaching the silicon surface and etching of the oxide surface. The silicon dioxide protects the silicon surface from plasma damage and from contamination.
摘要翻译：描述了等离子体工艺，其通过通过表面氧化物层的连续氧化和暴露的氧化硅表面的同时蚀刻消耗硅来产生未损坏和未污染的硅表面。表面二氧化硅层的厚度被控制为从氧原子到达硅表面的氧化物生长与氧化物表面的蚀刻之间的平衡。二氧化硅保护硅表面免受等离子体损伤和污染。

5. 发明授权

US6030874A Doped polysilicon to retard boron diffusion into and through thin gate dielectrics 失效
标题翻译：掺杂的多晶硅以阻止硼扩散进入并通过薄栅极电介质
公开(公告)号：US6030874A
公开(公告)日：2000-02-29
申请号：US7060
申请日：1998-01-13
申请人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
发明人： Douglas T. Grider , Stanton P. Ashburn , Katherine E. Violette , F. Scott Johnson
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/28035 , H01L21/2807 , H01L21/28176 , H01L21/32155 , H01L21/823842 , H01L29/4916 , H01L29/4966 , H01L21/28194 , H01L21/28202 , H01L29/518
摘要： An embodiment of the instant invention is a method of fabricating a semiconductor device which includes a dielectric layer situated between a conductive structure and a semiconductor substrate, the method comprising the steps of: forming the dielectric layer (layer 14) on the semiconductor substrate (substrate 12); forming the conductive structure (structure 18) on the dielectric layer; doping the conductive structure with boron; and doping the conductive structure with a dopant which inhibits the diffusion of boron. The semiconductor device may be a PMOS transistor or a capacitor. Preferably, the conductive structure is a gate structure. The dielectric layer is, preferably, comprised of a material selected from the group consisting of: an oxide, an oxide/oxide stack, an oxide/nitride stack, and an oxynitride. Preferably, the dopant which inhibits the diffusion of boron comprises at least one group III or group IV element. More specifically, it is preferably comprised of: carbon, germanium, and any combination thereof. Preferably, the steps of doping the conductive structure with boron and doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously, or the step of doping the conductive structure with boron is preformed prior to the step of doping the conductive structure with a dopant which inhibits the diffusion of boron are accomplished substantially simultaneously.
摘要翻译：本发明的实施例是一种制造半导体器件的方法，该半导体器件包括位于导电结构和半导体衬底之间的电介质层，该方法包括以下步骤：在半导体衬底（衬底）上形成介电层（层14） 12）; 在电介质层上形成导电结构（结构18）; 用硼掺杂导电结构; 并用抑制硼扩散的掺杂剂掺杂导电结构。半导体器件可以是PMOS晶体管或电容器。优选地，导电结构是栅极结构。电介质层优选由选自氧化物，氧化物/氧化物堆，氧化物/氮化物叠层和氧氮化物的材料组成。优选地，抑制硼扩散的掺杂剂包含至少一个III族或IV族元素。更具体地，其优选包括：碳，锗及其任何组合。优选地，用硼掺杂导电结构并用抑制硼的扩散的掺杂剂掺杂导电结构的步骤基本上同时实现，或者在掺杂导电的步骤之前预先形成用硼掺杂导电结构的步骤具有抑制硼扩散的掺杂剂的结构基本上同时完成。

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