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1. 发明申请

US20040113230A1 Self-aligned STI for narrow trenches 有权
公开(公告)号：US20040113230A1
公开(公告)日：2004-06-17
申请号：US10722353
申请日：2003-11-25
申请人： International Business Machines Corporation
发明人： Ramachandra Divakaruni , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L021/336 , H01L029/00
CPC分类号： H01L27/10867 , H01L21/76232 , H01L21/76235 , H01L27/0207 , H01L27/10864
摘要： A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.

2. 发明申请

US20040113207A1 Vertical MOSFET SRAM cell 失效
标题翻译：垂直MOSFET SRAM单元
公开(公告)号：US20040113207A1
公开(公告)日：2004-06-17
申请号：US10318495
申请日：2002-12-11
申请人： International Business Machines Corporation
发明人： Louis L. Hsu , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L021/00 , H01L021/8244 , H01L029/76 , H01L031/062 , H01L031/119
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译：形成SRAM单元装置的方法包括以下步骤。形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到到共同的身体层。形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。然后，连接FET晶体管以形成SRAM单元。

3. 发明申请

US20020105019A1 Structure and method for a compact trench-capacitor DRAM cell with body contact 失效
标题翻译：具有身体接触的紧凑型沟槽电容器DRAM单元的结构和方法
公开(公告)号：US20020105019A1
公开(公告)日：2002-08-08
申请号：US09777576
申请日：2001-02-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L027/108
CPC分类号： H01L27/10864 , H01L27/0214 , H01L27/1203
摘要： A compact DRAM cell array that substantially minimizes floating-body effects and device-to-device interactions is disclosed. The compact DRAM cell array includes a plurality of annular memory cells that are arranged in rows and columns. Each annular memory cell includes a vertical MOSFET and an underlying capacitor that are in electrical contact to each other through a buried-strap outdiffusion region which is present within a portion of a wall of each annular memory cell such that the portion partially encircles the wall. The remaining portions of the wall of each annular memory cell have a body contact region that serves to electrically connect the annular memory cell to an adjacent array well region. The DRAM cell array also includes a plurality of wordlines overlaying the vertical MOSFETs, and a plurality of bitlines that are orthogonal to the plurality of wordlines.
摘要翻译：公开了一种紧凑的DRAM单元阵列，其基本上最小化了浮体效应和器件到器件的相互作用。紧凑型DRAM单元阵列包括以行和列排列的多个环形存储单元。每个环形存储单元包括垂直MOSFET和底层电容器，其通过存在于每个环形存储器单元的壁的一部分内的掩埋带外扩散区域彼此电接触，使得该部分部分地围绕壁。每个环形存储单元的壁的剩余部分具有用于将环形存储器单元电连接到相邻阵列阱区的主体接触区域。 DRAM单元阵列还包括覆盖垂直MOSFET的多个字线以及与多个字线正交的多个位线。

4. 发明申请

US20040248356A1 Low-GIDL MOSFET structure and method for fabrication 失效
公开(公告)号：US20040248356A1
公开(公告)日：2004-12-09
申请号：US10876873
申请日：2004-06-25
申请人： International Business Machines Corporation
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L021/336 , H01L031/062
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

5. 发明申请

US20040135212A1 DAMASCENE METHOD FOR IMPROVED MOS TRANSISTOR 失效
标题翻译：改进的MOS晶体管的改进方法
公开(公告)号：US20040135212A1
公开(公告)日：2004-07-15
申请号：US10342423
申请日：2003-01-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L021/336
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

6. 发明申请

US20030008526A1 Method of forming variable oxide thicknesses across semiconductor chips 审中-公开
标题翻译：在半导体芯片上形成可变氧化物厚度的方法
公开(公告)号：US20030008526A1
公开(公告)日：2003-01-09
申请号：US09760954
申请日：2001-01-16
申请人： International Business Machines Corporation
发明人： Jeffrey P. Gambino , Gary B. Bronner , Carl J. Radens
IPC分类号： H01L021/31 , H01L021/469
CPC分类号： H01L21/0214 , H01L21/0223 , H01L21/02238 , H01L21/31116 , H01L21/31662 , H01L21/3185 , H01L27/10873 , H01L27/10897
摘要： A method for protecting selected first surfaces on a semiconductor substrate during application of a second oxide layer to said substrate comprising applying an oxidation barrier layer as a mask over said selected first surfaces, prior to patterning said semiconductor substrate with a resist mask and applying said second oxide layer.
摘要翻译：一种用于在向所述衬底施加第二氧化物层期间保护半导体衬底上所选择的第一表面的方法，包括在用抗蚀剂掩模对所述半导体衬底进行图案化之前，在所述选定的第一表面上施加氧化阻挡层作为掩模，氧化层。

7. 发明申请

US20020100945A1 Method for delineation of eDRAM support device notched gate 有权
标题翻译： eDRAM支持设备缺口门的描述方法
公开(公告)号：US20020100945A1
公开(公告)日：2002-08-01
申请号：US09772345
申请日：2001-01-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L021/336 , H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： H01L27/10873 , H01L21/28114 , H01L21/28123 , H01L21/82385 , H01L21/823864 , H01L27/10891 , H01L27/10894
摘要： A complementary metal oxide semiconductor integrated circuit containing a notched gate in the support device region as well as a method of forming the same are provided. The method of the present invention includes the steps of (a) forming a gate stack on a surface of a substrate, the gate stack including at least a gate dielectric having a gate conductor formed thereon and the substrate includes array device regions and support device regions; (b) protecting portions of the gate stack in the array and support device regions, while leaving other portions of the gate stack exposed; (c) partially etching the exposed portions of the gate stack so as to remove some, but not all, of the gate conductor; (d) forming a gapfill film on the protected gate stack and on the partially etched gate stack in the array and support device regions; (e) removing the gapfill film from the support device regions, while selectively removing the gapfill film from the array device regions so as to leave gapfill film between adjacent protected gate stacks; (f) forming spacers on any exposed sidewalls of the protected gate stacks; (g) removing exposed gate conductor in the array and support device regions; (h) providing an undercut in lower exposed regions of remaining gate conductor; and (i) removing remaining gapfill film from adjacent protected gate stacks in the array device region.
摘要翻译：提供了一种在支撑装置区域中包含缺口栅的互补金属氧化物半导体集成电路及其形成方法。本发明的方法包括以下步骤：（a）在衬底的表面上形成栅极叠层，所述栅极堆叠至少包括形成在其上的栅极导体的栅极电介质，并且所述衬底包括阵列器件区域和支撑器件区域 ; （b）保护阵列中的栅极堆叠的部分和支撑装置区域，同时使栅堆叠的其它部分露出; （c）部分地蚀刻栅极堆叠的暴露部分，以去除栅极导体中的一些但不是全部的; （d）在保护的栅极堆叠和阵列和支撑装置区域中的部分蚀刻的栅极堆叠上形成间隙填充膜; （e）从所述支撑装置区域移除所述间隙填充膜，同时从所述阵列装置区域选择性地移除所述间隙填充膜，以便在相邻的受保护栅极堆叠之间留下间隙填充膜; （f）在受保护的栅极堆叠的任何暴露的侧壁上形成间隔物; （g）去除阵列中的暴露的栅极导体和支撑装置区域; （h）在剩余栅极导体的下暴露区域中提供底切; 和（i）从阵列器件区域中的相邻受保护栅极堆叠中去除剩余的间隙填充膜。

8. 发明申请

US20010036750A1 Dual damascene anti-fuse with via before wire 失效
标题翻译：双镶嵌反熔丝与导线之间通孔
公开(公告)号：US20010036750A1
公开(公告)日：2001-11-01
申请号：US09873537
申请日：2001-06-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Carl J. Radens , Axel C. Brintzinger
IPC分类号： H01L021/31
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which a patterned anti-fuse material is formed therein comprising: a substrate having a first level of electrically conductive features; a patterned anti-fuse material formed on said substrate, wherein said patterned anti-fuse material includes an opening to at least one of said first level of electrically conductive features; a patterned interlevel dielectric material formed on said patterned anti-fuse material, wherein said patterned interlevel dielectric includes vias, as least one of said vias includes a via space; and a second level of electrically conductive features formed in said vias and via spaces.
摘要翻译：其中形成图案化的反熔丝材料的互连结构包括：具有第一级导电特征的衬底; 形成在所述衬底上的图案化反熔丝材料，其中所述图案化的抗熔丝材料包括至少一个所述第一级导电特征的开口; 形成在所述图案化反熔丝材料上的图案化层间介电材料，其中所述图案化层间电介质包括通孔，所述通孔中至少一个包括通孔空间; 以及形成在所述通孔和通孔空间中的第二级导电特征。

9. 发明申请

US20040180492A1 Method for forming dual workfunction high-performance support MOSFETs in EDRAM arrays 审中-公开
标题翻译：在EDRAM阵列中形成双功能高性能支持MOSFET的方法
公开(公告)号：US20040180492A1
公开(公告)日：2004-09-16
申请号：US10812283
申请日：2004-03-29
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Jack A. Mandelman , Ramachandra Divakaruni , Carl J. Radens
IPC分类号： H01L021/8244
CPC分类号： H01L27/10864 , H01L27/10894 , H01L27/10897
摘要： Methods of preparing dual workfunction high-performance support metal oxide semiconductor field effect transistor (MOSFETs)/embedded dynamic random access (EDRAM) arrays are provided. The methods describe herein reduce the number of deep-UV masks used in forming the memory structure, decouple the support and arraying processing steps, provide salicided gates, source/drain regions and bitlines, and provide, in some instances, local interconnects at no additional processing costs. Dual workfunction high-performance support MOSFETs/EDRAM, arrays having a gate conductor guard ring and/or local interconnections are also provided.
摘要翻译：提供双功能功能高性能支持金属氧化物半导体场效应晶体管（MOSFET）/嵌入式动态随机存取（EDRAM）阵列的方法。本文描述的方法减少了在形成存储器结构中使用的深UV掩模的数量，解耦支持和排列处理步骤，提供盐化栅极，源极/漏极区域和位线，并且在一些情况下提供局部互连，加工成本。还提供双功能功能高性能支持MOSFET / EDRAM，具有栅极导体保护环和/或局部互连的阵列。

10. 发明申请

US20030155599A1 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US20030155599A1
公开(公告)日：2003-08-21
申请号：US09683831
申请日：2002-02-21
申请人： International Business Machines Corporation
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L027/108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

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