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1. 发明申请

US20040241955A1 METHOD OF FABRICATING SHALLOW TRENCH ISOLATION BY ULTRA-THIN SIMOX PROCESSING 失效
标题翻译：通过超薄薄膜加工制造薄壁分离分离方法
公开(公告)号：US20040241955A1
公开(公告)日：2004-12-02
申请号：US10250053
申请日：2003-05-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bruce B. Doris , Mark C. Hakey , Akihisa Sekiguchi
IPC分类号： H01L021/76
CPC分类号： H01L21/76237 , H01L21/76243 , H01L21/76267
摘要： The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.
摘要翻译：本发明提供了在半导体衬底中形成隔离区域（例如浅沟槽隔离区域）的成本有效和简单的方法，其避免了蚀刻到沟槽中。在本发明中，通过利用在衬底的上表面附近产生氧注入区的选择性离子注入工艺来形成隔离区。在随后的退火步骤中，氧注入区域被转换成具有与衬底的上表面基本上共面的上表面的隔离区域。

2. 发明申请

US20030199166A1 Structure and method to preserve STI during etching 审中-公开
公开(公告)号：US20030199166A1
公开(公告)日：2003-10-23
申请号：US10437370
申请日：2003-05-13
申请人： International Business Machines Corporation
发明人： Omer H. Dokumaci , Bruce B. Doris
IPC分类号： H01L021/302 , H01L021/461
CPC分类号： H01L21/02271 , H01L21/02118 , H01L21/0217 , H01L21/02211 , H01L21/31144 , H01L21/3185 , H01L21/76224 , H01L21/76283
摘要： Disclosed is a method of protecting a semiconductor shallow trench isolation (STI) oxide from etching, the method comprising lowering, if necessary, the upper surface of said STI oxide to a level below that of adjacent silicon active areas, depositing a nitride liner upon said STI oxide and adjacent silicon active areas in a manner effective in defining a depression above said STI oxide, filling said depression with a protective film, and removing said nitride layer from said adjacent active areas.

3. 发明申请

US20030010972A1 METHOD OF IMPROVING GATE ACTIVATION BY EMPLOYING ATOMIC OXYGEN ENHANCED OXIDATION 失效
标题翻译：通过使用原子氧增强氧化来改善门控活化的方法
公开(公告)号：US20030010972A1
公开(公告)日：2003-01-16
申请号：US09905233
申请日：2001-07-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Atul C. Ajmera , Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov
IPC分类号： H01L027/01 , H01L031/0392 , H01L029/06
CPC分类号： H01L21/28035 , H01L21/32105 , H01L29/4916
摘要： The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0.1, preferably 0.05, nullm or less.
摘要翻译：本发明提供一种制备Si基金属 - 绝缘体半导体（MIS）晶体管的方法，其通过降低侧壁氧化工艺的热量预算来防止栅极导体的多晶晶粒变得明显更大。通过利用原子氧作为氧化环境，本发明的侧壁氧化过程的热预算比常规现有技术的侧壁氧化过程减少一到两个数量级。本发明还提供具有晶体尺寸为约0.1μm，优选0.05μm或更小的栅极导体的Si基MIS晶体管。

4. 发明申请

US20040023500A1 Method for blocking implants from the gate of an electronic device via planarizing films 失效
公开(公告)号：US20040023500A1
公开(公告)日：2004-02-05
申请号：US10212938
申请日：2002-08-05
申请人： International Business Machines Corporation
发明人： Omer H. Dokumaci , Bruce B. Doris
IPC分类号： H01L021/311
CPC分类号： H01L29/66545 , H01L21/31051 , H01L21/31111 , H01L21/31116 , H01L21/312 , H01L21/3144 , H01L21/31612 , H01L21/3185
摘要： A method is provided for blocking implants from the gate electrode of an FET device. Form a first planarizing film covering the substrate and the gate electrode stack. The first planarizing film is planarized by either polishing or self-planarizing. For deposition by HDP or use of spin on materials, the film is self-planarizing. Where polishing is required, the first planarizing film is planarized by polishing until the top of the gate electrode is exposed. Etch back the gate electrode below the level of the upper surface of the first planarizing film. Then deposit a blanket layer of a second planarizing film and polish to planarize it to a level exposing the first planarizing film, forming the second planarizing film into an implantation block covering the top surface of the gate. Remove the first planarizing film. Form the counterdoped regions by implanting dopant into the substrate using the implantation block to block implantation of the dopant into the gate electrode. The implantation block protects the gate electrode of the FET from unwanted implanted impurities during implanting of the counterdoped regions. The first planarizing film is composed of a material selected from the group consisting of HDP (high density plasma) silicon oxide and HDP silicon nitride, an interlevel-dielectric layer material including ONO, and photoresist. The gate electrode is composed of a material selected from the group consisting of polysilicon and metal. The second planarizing film comprises a material such as HDP oxide, HDP nitride, and an organic layer including ARCs. The second planarizing film comprises a different material from the first planarizing film.

5. 发明申请

US20030038109A1 Method of making thermally stable planarizing films 失效
标题翻译：制造热稳定平面化膜的方法
公开(公告)号：US20030038109A1
公开(公告)日：2003-02-27
申请号：US09938097
申请日：2001-08-23
申请人： International Business Machines Corporation, Armonk, New York,
发明人： Omer H. Dokumaci , Bruce B. Doris , Michael P. Belyansky
IPC分类号： H01L021/302
CPC分类号： H01L21/76819 , H01L21/31056
摘要： Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon oxide and silicon nitride, depositing a planarized polymer film to a thickness effective in protecting said high density plasma film while leaving high density plasma excess exposed, and etching away said high density plasma excess.
摘要翻译：公开了一种在暴露半导体表面处理结构的同时保护半导体区域的方法，该方法包括沉积选自硅氧化物和氮化硅的硅化合物的平面化高密度等离子体膜，将平坦化的聚合物膜沉积到有效地保护所述高密度等离子体膜同时留下高密度等离子体过剩暴露的厚度，并蚀刻掉所述高密度等离子体过剩。

6. 发明申请

US20030011080A1 METHOD OF FABRICATING SIO2 SPACERS AND ANNEALING CAPS 有权
标题翻译：制备SIO2间隔物和退火CAPS的方法
公开(公告)号：US20030011080A1
公开(公告)日：2003-01-16
申请号：US09902830
申请日：2001-07-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sadanand V. Deshpande , Bruce B. Doris , Rajarao Jammy , William H. Ma
IPC分类号： H01L021/338 , H01L021/8238
CPC分类号： H01L29/6659 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/7833
摘要： Divot fill methods of incorporating thin SiO2 spacer and/or annealing caps into a complementary metal oxide semiconductor (CMOS) processing flow are provided. In accordance with the present invention, the divot fill processes provide a means for protecting the exposed surfaces of the thin SiO2 spacer and/or annealing cap such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning step. CMOS devices including thin SiO2 spacer and/or annealing caps whose surfaces are protected such that those surfaces are not capable of being attacked by a subsequent silicide pre-cleaning or other process steps are also provided.
摘要翻译：提供了将薄SiO 2间隔物和/或退火帽并入互补金属氧化物半导体（CMOS）处理流程中的填充方法。根据本发明，凹坑填充方法提供了用于保护薄SiO 2间隔物和/或退火盖的暴露表面的装置，使得那些表面不能被随后的硅化物预清洁步骤攻击。还提供了包括薄SiO 2间隔物和/或退火帽的CMOS器件，其表面被保护，使得那些表面不能被后续的硅化物预清洁或其它工艺步骤所攻击。

7. 发明申请

US20040248356A1 Low-GIDL MOSFET structure and method for fabrication 失效
公开(公告)号：US20040248356A1
公开(公告)日：2004-12-09
申请号：US10876873
申请日：2004-06-25
申请人： International Business Machines Corporation
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L021/336 , H01L031/062
CPC分类号： H01L29/4983 , H01L21/26586 , H01L21/28105 , H01L29/66484 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7831 , H01L29/7836 , Y10S257/90
摘要： A low-GIDL current MOSFET device structure and a method of fabrication thereof which provides a low-GIDL current. The MOSFET device structure contains a central gate conductor whose edges may slightly overlap the source/drain diffusions, and left and right side wing gate conductors which are separated from the central gate conductor by a thin insulating and diffusion barrier layer.

8. 发明申请

US20040242010A1 STI STRESS MODIFICATION BY NITROGEN PLASMA TREATMENT FOR IMPROVING PERFORMANCE IN SMALL WIDTH DEVICES 失效
标题翻译：用于改善小宽度装置性能的硝基等离子体处理的STI应力变化
公开(公告)号：US20040242010A1
公开(公告)日：2004-12-02
申请号：US10250047
申请日：2003-05-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sadanand V. Deshpande , Bruce B. Doris , Werner A. Rausch , James A. Slinkman
IPC分类号： H01L021/302
CPC分类号： H01L29/7842 , H01L21/3185 , H01L21/76237 , H01L29/1033
摘要： A method for modulating the stress caused by bird beak formation of small width devices by a nitrogen plasma treatment. The nitrogen plasma process forms a nitride liner about the trench walls that serves to prevent the formation of bird beaks in the isolation region during a subsequent oxidation step. In one embodiment, the plasma nitridation process occurs after trench etching, but prior to trench fill. In yet another embodiment, the plasma nitridation process occurs after trench fill. In yet another embodiment, a block mask is formed over predetermined active areas of the etched substrate prior to the plasma nitridation process. This embodiment is used in protecting the PFET device area from the plasma nitridation process thereby providing a means to form a PFET device area in which stress caused by bird beak formation increases the device performance of the PFET.
摘要翻译：一种通过氮等离子体处理调节小宽度装置的鸟嘴形成引起的应力的方法。氮等离子体工艺形成围绕沟槽壁的氮化物衬垫，其用于在随后的氧化步骤期间防止在隔离区中形成鸟嘴。在一个实施例中，等离子体氮化处理发生在沟槽蚀刻之后，但在沟槽填充之前。在另一个实施例中，等离子体氮化处理发生在沟槽填充之后。在另一个实施例中，在等离子体氮化处理之前，在蚀刻的衬底的预定有效区域上形成块掩模。该实施例用于保护PFET器件区域免受等离子体氮化处理，从而提供形成PFET器件区域的装置，其中由鸟嘴形成引起的应力增加了PFET的器件性能。

9. 发明申请

US20040241981A1 STRUCTURE AND METHOD TO FABRICATE ULTRA-THIN Si CHANNEL DEVICES 失效
标题翻译：用于织造超薄Si沟道器件的结构和方法
公开(公告)号：US20040241981A1
公开(公告)日：2004-12-02
申请号：US10250069
申请日：2003-06-02
申请人： International Business Machines Corporation
发明人： Bruce B. Doris , Thomas S. Kanarsky , Meikei Ieong , Wesley C. Natzle
IPC分类号： H01L021/4763
CPC分类号： H01L21/84 , H01L21/76283
摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.
摘要翻译：提供了一种用于防止在隔离的超薄Si沟道器件的有源器件区域下形成多晶硅的方法。该方法使用化学氧化物去除（COR）处理步骤来防止托管架形成，而不是采用诸如HF的化学蚀刻剂的常规湿法蚀刻工艺。还提供了绝缘体上硅（SOI）结构。该结构包括至少位于掩埋绝缘层上的顶部含Si层; 以及位于顶部含Si层和掩埋绝缘层的一部分中的氧化物填充沟槽隔离区。顶部含Si层下方没有底切区域。

10. 发明申请

US20040135212A1 DAMASCENE METHOD FOR IMPROVED MOS TRANSISTOR 失效
标题翻译：改进的MOS晶体管的改进方法
公开(公告)号：US20040135212A1
公开(公告)日：2004-07-15
申请号：US10342423
申请日：2003-01-14
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Omer H. Dokumaci , Bruce B. Doris , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L021/336
CPC分类号： H01L29/66583 , H01L21/26586 , H01L21/28114 , H01L29/665 , H01L29/66553
摘要： A MOSFET fabrication methodology and device structure, exhibiting improved gate activation characteristics. The gate doping that may be introduced while the source drain regions are protected by a damascene mandrel to allow for a very high doping in the gate conductors, without excessively forming deep source/drain diffusions. The high gate conductor doping minimizes the effects of electrical depletion of carriers in the gate conductor. The MOSFET fabrication methodology and device structure further results in a device having a lower gate conductor width less than the minimum lithographic minimum image, and a wider upper gate conductor portion width which may be greater than the minimum lithographic image. Since the effective channel length of the MOSFET is defined by the length of the lower gate portion, and the line resistance is determined by the width of the upper gate portion, both short channel performance and low gate resistance are satisfied simultaneously.
摘要翻译： MOSFET制造方法和器件结构，表现出改进的栅极激活特性。当源极漏极区域被镶嵌心轴保护以允许栅极导体中的非常高的掺杂而不会过度地形成深的源极/漏极扩散时，可以引入栅极掺杂。高栅极导体掺杂最大限度地减小了栅极导体中载流子的电耗损的影响。 MOSFET制造方法和器件结构进一步导致具有小于最小光刻最小图像的较低栅极导体宽度的器件，以及可能大于最小光刻图像的较宽上部栅极导体部分宽度。由于MOSFET的有效沟道长度由下栅极部分的长度限定，并且线路电阻由上部栅极部分的宽度决定，所以同时满足短沟道性能和低栅极电阻。

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