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1. 发明申请

US20040262647A1 Variable threshold voltage complementary MOSFET with SOI structure 有权
标题翻译：具有SOI结构的可变阈值电压互补MOSFET
公开(公告)号：US20040262647A1
公开(公告)日：2004-12-30
申请号：US10739200
申请日：2003-12-19
发明人： Masao Okihara
IPC分类号： H01L031/119
CPC分类号： H01L27/1203
摘要： The dependency of threshold voltage on adjusted bias voltage is varied between an N-channel MOSFET and a P-channel MOSFET. A support substrate, an insulating layer disposed on the support substrate, and island-shaped first and second silicon layers separately formed on the insulating layer; a first MOSFET formed of a fully depleted SOI where a first channel part is formed in the first silicon layer; and a second MOSFET formed of a partially depleted SOI where a second channel part is formed in the second silicon layer, the second MOSFET configures a complementary MOSFET with the first MOSFET, are provided. The threshold voltage of the second MOSFET formed of the partially depleted SOI is hardly varied because of a neutral region disposed in the second channel part, even though bias voltage is applied to the support substrate to vary the threshold voltage of the first MOSFET formed of the fully depleted SOI.
摘要翻译：阈值电压对调整偏置电压的依赖性在N沟道MOSFET和P沟道MOSFET之间变化。支撑基板，设置在支撑基板上的绝缘层和分别形成在绝缘层上的岛状的第一和第二硅层; 由完全耗尽的SOI形成的第一MOSFET，其中第一沟道部分形成在第一硅层中; 以及由部分耗尽的SOI形成的第二MOSFET，其中第二沟道部分形成在第二硅层中，第二MOSFET配置与第一MOSFET的互补MOSFET。由于部分耗尽的SOI形成的第二MOSFET的阈值电压几乎不变，因为即使将偏置电压施加到支撑衬底上以改变由第二沟道部分形成的第一MOSFET的阈值电压，完全耗尽SOI。

2. 发明申请

US20040256646A1 High voltage MOSFET and method of fabricating the same 失效
标题翻译：高压MOSFET及其制造方法
公开(公告)号：US20040256646A1
公开(公告)日：2004-12-23
申请号：US10860295
申请日：2004-06-03
发明人： Sun-hak Lee , Kwang-dong Yoo
IPC分类号： H01L021/336 , H01L029/76 , H01L031/062 , H01L021/4763 , H01L031/119
CPC分类号： H01L29/66613 , H01L29/1083 , H01L29/7833
摘要： A MOSFET includes an insulated gate electrode on a surface of a semiconductor substrate having an impurity region of first conductivity type therein that extends to the surface. Source and drain regions of second conductivity type are provided in the impurity region. The source region includes a highly doped source contract region that extends to the surface and a lightly doped source extension. The lightly doped source extension extends laterally underneath a first end of the insulated gate electrode and defines a source-side P-N junction with the well region. The drain region includes a highly doped drain contact region that extends to the surface and a lightly doped drain extension. The lightly doped drain extension extends laterally underneath a second end of the insulated gate electrode and defines a drain-side P-N junction with the well region. This well region, which extends within the impurity region and defines a non-rectifying junction therewith, is more highly doped than the impurity region. The well region extends opposite the insulated gate electrode and has a sufficient width that dopants therein partially compensate innermost portions of the lightly doped source and drain extensions that extend underneath the insulated gate electrode. However, the well region is not so wide as to provide compensation to remaining portions of the lightly doped source and drain extensions or the source and drain contact regions.
摘要翻译： MOSFET在半导体衬底的表面上具有绝缘栅电极，其中具有第一导电类型的杂质区延伸到表面。第二导电类型的源区和漏区设置在杂质区中。源极区域包括延伸到表面的高掺杂源极接合区域和轻掺杂源极延伸部分。轻掺杂源极延伸部在绝缘栅电极的第一端下方横向延伸，并且与阱区域限定源极侧P-N结。漏极区域包括延伸到表面的高度掺杂的漏极接触区域和轻掺杂漏极延伸部分。轻掺杂的漏极延伸部在绝缘栅电极的第二端下方横向延伸，并且与阱区域限定漏极侧P-N结。在杂质区域内延伸并且与其限定非整流结的阱区域比杂质区域更高掺杂。阱区域与绝缘栅电极相对延伸并且具有足够的宽度，其中的掺杂剂部分地补偿在绝缘栅电极下方延伸的轻掺杂源极和漏极延伸部分的最内部分。然而，阱区域不是如此宽，以便为轻掺杂源极和漏极延伸部分或源极和漏极接触区域的剩余部分提供补偿。

3. 发明申请

US20040238899A1 Integrated semiconductor memory and method for reducing leakage currents in an integrated semiconductor memory 失效
标题翻译：用于减少集成半导体存储器中的漏电流的集成半导体存储器和方法
公开(公告)号：US20040238899A1
公开(公告)日：2004-12-02
申请号：US10843318
申请日：2004-05-12
发明人： Helmut Fischer , Jens Egerer
IPC分类号： H01L031/119
CPC分类号： G11C29/02 , G11C2029/5006
摘要： An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.
摘要翻译：集成半导体存储器可以包括布置在非重叠区域部分上的多个子电路块。每个子电路块具有块供电线和块接地线，其为电路中的各个电路块的各个开关元件提供电压。每个块供电线和块接地线连接到芯片供电线和芯片接地线，其在子电路块的区域外延伸。至少一个子电路块的芯片供给线和块供应线之间或至少一个子电路块的芯片接地线和块接地线之间的至少一个连接可以由开关器件隔离。此外，一种减少半导体存储器中漏电流的方法，其取决于半导体存储器的工作状态，将半导体存储器的各个子电路块与电压源隔离或连接。

4. 发明申请

US20040206989A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20040206989A1
公开(公告)日：2004-10-21
申请号：US10606755
申请日：2003-06-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Satoshi Aida , Shigeo Kouzuki , Masaru Izumisawa , Hironori Yoshioka , Wataru Saito
IPC分类号： H01L029/80 , H01L031/112 , H01L031/119
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/0653 , H01L29/0696 , H01L29/7802
摘要： A semiconductor device includes: a semiconductor substrate of a first conductivity type; a semiconductor layer of a first conductivity type formed on a first main surface of the semiconductor substrate, the semiconductor layer including a first region for a cell portion and a second region for a terminating portion, the second region being positioned in an outer periphery of the first region, the terminating portion maintaining breakdown voltage by extending a depletion layer to relieve an electric field; junction pairs of semiconductor layers periodically arranged so as to form a line from the first region to the second region in a first direction parallel to the first main surface in the semiconductor layer and having mutually opposite conductivity types of impurities, each of the junction pair being composed of a first impurity diffusion layer of a second conductivity type formed from a surface of the semiconductor layer toward the semiconductor substrate and a second impurity diffusion layer of a first conductivity type formed from the surface of the semiconductor layer toward the semiconductor substrate and adjacently to the first impurity diffusion layer; a base layer of a second conductivity type selectively formed on each surface layer of the junction pairs which are formed in the first region, so as to connect with the first impurity diffusion layer and the second impurity diffusion layer in the same manner; a source layer of a first conductivity type selectively formed on each surface layer of the base layers of the second conductive type; a control electrode formed above each surface of the base layers and above each surface of the source layers via an insulating film; a first main electrode formed so as to cover the control electrode and to contact the source layers and the base layers in the same manner; and a second main electrode formed on a second main surface opposite to the first main surface of the semiconductor substrate.
摘要翻译：半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的第一主表面上的第一导电类型的半导体层，所述半导体层包括用于单元部分的第一区域和用于端接部分的第二区域，所述第二区域位于所述半导体衬底的外周中第一区域，终端部分通过延伸耗尽层来缓和电场来保持击穿电压; 在半导体层中平行于第一主表面的第一方向上并且具有相互相反的导电类型的杂质的周期性地布置以便形成从第一区域到第二区域的线的结对对，由半导体层的朝向半导体衬底的表面形成的第二导电类型的第一杂质扩散层和由半导体层的表面朝向半导体衬底形成的第一导电类型的第二杂质扩散层，并且相邻于第一杂质扩散层; 选择性地形成在形成在第一区域的结对的每个表面层上的第二导电类型的基底层，以与第一杂质扩散层和第二杂质扩散层相同的方式连接; 选择性地形成在第二导电类型的基底层的每个表面层上的第一导电类型的源极层; 控制电极，其经由绝缘膜形成在所述基底层的每个表面上方和所述源极层的每个表面上方; 形成为覆盖控制电极并以相同的方式接触源极层和基极层的第一主电极; 以及形成在与所述半导体衬底的所述第一主表面相对的第二主表面上的第二主电极。

5. 发明申请

US20040195613A1 Semiconductor memory device capable of preventing oxidation of plug and method for fabricating the same 有权
标题翻译：能够防止插头氧化的半导体存储装置及其制造方法
公开(公告)号：US20040195613A1
公开(公告)日：2004-10-07
申请号：US10828206
申请日：2004-04-21
申请人： Hynix Semiconductor Inc.
发明人： Soon-Yong Kweon
IPC分类号： H01L027/108 , H01L029/76 , H01L029/94 , H01L031/119 , H01L023/48
CPC分类号： H01L21/7687 , H01L21/76877 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.
摘要翻译：半导体器件及其制造方法提供一种插塞结构，该插塞结构由形成在接触孔的底部和侧面的扩散阻挡层和形成在扩散阻挡层上的氧化阻挡层组成，该氧化阻挡层填满接触孔的内部。本发明防止底电极和插头的接触电阻增加以及实现高速操作并提高半导体器件的可靠性。

6. 发明申请

US20040175881A1 Static pass transistor logic with transistors with multiple vertical gates 失效
标题翻译：具有多个垂直栅极的晶体管的静态晶体管逻辑
公开(公告)号：US20040175881A1
公开(公告)日：2004-09-09
申请号：US10790510
申请日：2004-03-01
申请人： Micron Technology, Inc.
发明人： Leonard Forbes , Kie Y. Ahn
IPC分类号： H01L029/94 , H01L029/76 , H01L031/119
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/1052 , H01L29/42332 , H01L29/7831 , H01L29/7887
摘要： Static pass transistor logic having transistors with multiple vertical gates are described. Multiple vertical gates are edge defined with only a single transistor being required for multiple logic inputs. Thus a minimal surface area is required for each logic input. The static pass transistor includes a transistor which has a horizontal depletion mode channel region between a single source and drain region. A number of vertical gates are located above different portions of the depletion mode channel region. A vertical gate is located above a first portion of the depletion mode channel region and is separated therefrom by a first insulator material. A vertical gate is located above a second portion of the channel region and is separated therefrom by a second insulator material. There is no source nor drain region associated with each input and the gates have sub-lithographic horizontal dimensions by virtue of being edge defined vertical gates.
摘要翻译：描述了具有多个垂直栅极的晶体管的静态晶体管逻辑。多个垂直栅极是边界限定的，多个逻辑输入只需要单个晶体管。因此，每个逻辑输入都需要最小的表面积。静态晶体管包括在单个源极和漏极区域之间具有水平耗尽模式沟道区的晶体管。多个垂直栅极位于耗尽模式沟道区的不同部分上方。垂直栅极位于耗尽模式沟道区的第一部分之上，并且通过第一绝缘体材料与其隔开。垂直门位于通道区域的第二部分上方，并通过第二绝缘体材料与其隔开。没有与每个输入相关联的源极和漏极区域，并且由于边缘限定的垂直栅极，栅极具有亚光刻水平尺寸。

7. 发明申请

US20040169211A1 AVOIDING SHORTING IN CAPACITORS 有权
标题翻译：避免电容短路
公开(公告)号：US20040169211A1
公开(公告)日：2004-09-02
申请号：US10248897
申请日：2003-02-28
发明人： Haoren Zhuang , Ulrich Egger , Jingyu Lian , Gerhard Beitel , Karl Hornik
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： H01L27/11502 , H01L27/0805 , H01L27/11507 , H01L28/55
摘要： A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor comprises an upper and lower portion. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.
摘要翻译：公开了一种电容器结构，其具有在顶部电极和底部电极之间具有顶部电极，底部电极和电容器电介质层的电容器。电容器包括上部和下部。上部和下部之间的分界位于电容器介电层的顶表面和底表面之间。在电容器的上部的侧壁上设置有电介质层，以防止在加工过程中形成的导电栅栏引起的电极之间短路。

8. 发明申请

US20040164333A1 Semiconductor devices and methods for manufacturing the same 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20040164333A1
公开(公告)日：2004-08-26
申请号：US10784387
申请日：2004-02-23
发明人： Hiroaki Tsugane , Hisakatsu Sato
IPC分类号： H01L021/336 , H01L029/76 , H01L027/108 , H01L031/119 , H01L029/00
CPC分类号： H01L27/10894 , H01L27/10814 , H01L27/10885
摘要： Certain embodiments of the present invention relate to a semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The semiconductor device includes an interlayer dielectric layer, an embedded connection layer and a connection layer, wherein the interlayer dielectric layer is located between the semiconductor substrate and the capacitor element. The connection layer and the embedded connection layer are used to electrically connect a lower electrode of the capacitor element to another semiconductor element. The connection layer is located in a common layer of a bit line that is a component of the DRAM. The embedded connection layer is located in a connection hole formed in the interlayer dielectric layer. One end of the embedded connection layer connects to the lower electrode at a bottom surface of the lower electrode, and another end of the embedded connection layer connects to the connection layer.
摘要翻译：本发明的某些实施例涉及一种半导体器件，其具有包括形成在半导体衬底的DRAM区域中的单元电容器的DRAM和形成在半导体衬底的模拟元件区域中的电容器元件。半导体器件包括层间介质层，嵌入式连接层和连接层，其中层间介质层位于半导体衬底和电容器元件之间。连接层和嵌入式连接层用于将电容器元件的下电极与另一个半导体元件电连接。连接层位于作为DRAM的组件的位线的公共层中。嵌入式连接层位于形成在层间电介质层中的连接孔中。嵌入式连接层的一端在下部电极的下表面与下部电极连接，嵌入式连接层的另一端与连接层连接。

9. 发明申请

US20040150020A1 Semiconductor device and method of producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20040150020A1
公开(公告)日：2004-08-05
申请号：US10648883
申请日：2003-08-27
申请人： Elpida Memory, Inc. , Hitachi, Ltd.
发明人： Satoru Yamada , Ryo Nagai , Kiyonori Oyu , Ryoichi Nakamura , Norikatsu Takaura
IPC分类号： H01L021/8238 , H01L029/76 , H01L031/119
CPC分类号： H01L27/10891 , H01L21/28061 , H01L21/823842 , H01L27/10894 , H01L27/10897 , H01L29/4941 , H01L29/7833
摘要： In a semiconductor device of a polysilicon gate electrode structure having three or more different Fermi levels, a P type polysilicon having a lowest Fermi level is disposed on a first N type surface channel MOS transistor. A first N type polysilicon having a highest Fermi level is disposed on a second N type surface channel MOS transistor. A second N type polysilicon having an intermediate Fermi level between the highest and the lowest Fermi levels and doped with both an N type impurity and a P type impurity is disposed on a P channel MOS transistor.
摘要翻译：在具有三个或更多个不同费米能级的多晶硅栅电极结构的半导体器件中，具有最低费米能级的P型多晶硅设置在第一N型表面沟道MOS晶体管上。具有最高费米能级的第一N型多晶硅被布置在第二N型表面沟道MOS晶体管上。具有最高和最低费米能级之间的中间费米能级并且掺杂有N型杂质和P型杂质的第二N型多晶硅设置在P沟道MOS晶体管上。

10. 发明申请

US20040119123A1 GAS INSULATED GATE FIELD EFFECT TRANSISTOR 失效
标题翻译：气体绝缘栅场效应晶体管
公开(公告)号：US20040119123A1
公开(公告)日：2004-06-24
申请号：US10324335
申请日：2002-12-19
发明人： Mark E. Murray
IPC分类号： H01L029/76 , H01L029/94 , H01L031/062 , H01L031/113 , H01L031/119
CPC分类号： H01L29/515 , H01L21/28167 , H01L29/78
摘要： The present invention relates to a gas insulated gate field effect transistor and a fabricating method thereof which provides an improved insulator between the gate and the source-drain channel of a field effect transistor. The insulator is a vacuum or a gas filled trench. As compared to a conventional MOSFET, the gas insulated gate device provides reduced capacitance between the gate and the source/drain region, improved device reliability and durability, and improved isolation from interference caused by nearby electric fields. The present invention includes the steps of forming a doped source region and drain region on a substrate, forming a gate, forming a gaseous gate insulating trench and forming terminals upon the gate, the source region and the drain region. A plurality of the devices on a single substrate may be combined to form an integrated circuit.
摘要翻译：气体绝缘栅场效应晶体管及其制造方法技术领域本发明涉及一种在场效应晶体管的栅极和源极 - 漏极沟道之间提供改进的绝缘体的气体绝缘栅场效应晶体管及其制造方法。绝缘体是真空或填充气体的沟槽。与常规MOSFET相比，气体绝缘栅极器件在栅极和源极/漏极区域之间提供降低的电容，改善器件可靠性和耐久性，以及改善与附近电场引起的干扰隔离。本发明包括以下步骤：在衬底上形成掺杂源极区和漏极区，形成栅极，形成气态栅绝缘沟槽，并在栅极，源极区和漏极区上形成端子。单个衬底上的多个器件可以组合以形成集成电路。

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